vector stuck message when using the IOAPIC
vector stuck message when using the IOAPIC
I'm trying to get interrupts from the IOAPIC working. Right now, I write 0 to the high portion of the IRQ1 IOAPIC register and 0x921 to the lower portion. When I run my OS in bochs, I receive no keyboard interrupts and the bochs console gets flooded with "vector 0x21 stuck?", nor do I receive any interrupts when running in QEMU. As far as I know, everything else is setup properly.
Re: vector stuck message when using the IOAPIC
You are setting up the IOAPIC incorrectly - setting bit 11 to 1 selects logical mode, in which case bits 56-63 are the message destination address (MDA). The interpretation of this depends on the destination format register in the local APICs of all processors in the system (it should be set the same for all enabled LAPICs). If using flat logical mode, then you assign one bit in the 8 bits at the end of the logical destination register (again on a per LAPIC basis) to each CPU and then select a group of them by setting the last 8 bits of the MDA to the logical address of each processor you wish to talk to.
e.g.
if you have 2 processors, set both LAPICs to flat mode, set the first LAPICs LDR to have bit 24 set and the second LAPICs LDR to have bit 25 set.
Then, to route an interrupt to the first CPU set the MDA (in the IOAPIC) to have bit 56 set.
To route an interrput to the second CPU set the MDA to have bit 57 set.
To route an interrupt to both (with the lowest priority one getting the interrupt) set bits 56 and 57 with delivery mode as 001
Your current setup is selecting logical mode for the interrupt with lowest priority delivery, but then not specifying any cpus to deliver the interrupt to. Options are either to properly set up logical mode (more difficult) or switch to physical mode, at which point a destination field of 0 will deliver to the BSP (which is easier and probably what you want at this point).
Regards,
John.
e.g.
if you have 2 processors, set both LAPICs to flat mode, set the first LAPICs LDR to have bit 24 set and the second LAPICs LDR to have bit 25 set.
Then, to route an interrupt to the first CPU set the MDA (in the IOAPIC) to have bit 56 set.
To route an interrput to the second CPU set the MDA to have bit 57 set.
To route an interrupt to both (with the lowest priority one getting the interrupt) set bits 56 and 57 with delivery mode as 001
Your current setup is selecting logical mode for the interrupt with lowest priority delivery, but then not specifying any cpus to deliver the interrupt to. Options are either to properly set up logical mode (more difficult) or switch to physical mode, at which point a destination field of 0 will deliver to the BSP (which is easier and probably what you want at this point).
Regards,
John.