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In "Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3A 9.9.2 Switching Back to Real-Address Mode", it says before we turn off the PE bit in CR0, we should:
Load segment registers SS, DS, ES, FS, and GS with a selector for a descriptor
containing the following values, which are appropriate for real-address mode:
— Limit = 64 KBytes (0FFFFH)
— Byte granular (G = 0)
— Expand up (E = 0)
— Writable (W = 1)
— Present (P = 1)
— Base = any value

Then, after we enter the real mode by turning of the PE bit in CR0, these segment registers shall also be updated:
Load the SS, DS, ES, FS, and GS registers as needed by the real-address mode
code. If any of the registers are not going to be used in real-address mode, write
0s to them.

The question is: why should we need a 16-bit segment? Couldn't we just set these segment registers to 0, after we enter the real mode?
Another question is: will the shadow register of these segment selector work in real mode? If so, which part(I mean, besides the segment base, will the segment limit part in the shadow register still work in real mode)?

Thanks!

Oh. Thanks!
So, I guess its main purpose is to set the limitation attribute in the shadow register(descriptor cache).
Now, I wonder if there's any other attribute that will be used in real mode besides the base and limit.