Random Single Step/Debug exception.
Posted: Sat Nov 26, 2011 3:37 pm
I am getting a random "Single Step/Debug" exception. I don't think it has anything to do with it, but I am currently testing my execute function, and am running in user mode. I have single stepped (no relation 
) through the loaded executables code and it executes just fine (right now it's just 3 instructions," mov %eax,SYSCALL_YIELD" and "int $0x80" then "jmp entry").
I read on the wiki that it could fire for a few different reasons, so I pulled up my intel manual. Sadly, my manual says that the Single Step/Debug exception (vector 1) is reserved.
Can someone give me some more information on when and why the Debug exception occurs?
Edit:
Found some more information on the debug registers. This page is helpful: http://www.logix.cz/michal/doc/i386/chp12-02.htm
I check DR6, bits 13-15. Bit 14 was set, and according to that page, this means it was a result of Trap Flag being set in EFLAGS, but I never set TF... I setup EFLAGS like so:
and inside the exception handler, it says EFLAGS from before the interrupt was 0x102, which is IF, and some reserved value that is always set by Intel. This all looks correct, but I'm still getting this exception. 
Is it safe to just ignore the debug exception? According to the wiki, it could be a fault, but I can't find documentation on how to determine that.
) through the loaded executables code and it executes just fine (right now it's just 3 instructions," mov %eax,SYSCALL_YIELD" and "int $0x80" then "jmp entry").I read on the wiki that it could fire for a few different reasons, so I pulled up my intel manual. Sadly, my manual says that the Single Step/Debug exception (vector 1) is reserved.
Can someone give me some more information on when and why the Debug exception occurs?
Edit:
Found some more information on the debug registers. This page is helpful: http://www.logix.cz/michal/doc/i386/chp12-02.htm
I check DR6, bits 13-15. Bit 14 was set, and according to that page, this means it was a result of Trap Flag being set in EFLAGS, but I never set TF... I setup EFLAGS like so:
Code: Select all
newreg->eflags = 0x102; // (IF | IOPL=0)Is it safe to just ignore the debug exception? According to the wiki, it could be a fault, but I can't find documentation on how to determine that.
