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Hey,

I have read some documents about the apic, io apic and msi. Also, I wrote some basic functions to write towards the apic, io apic + a function the read/write msi messages. I really want to build in MSI support since that is a quit clean method of building in PCI interrupt support.

But now I'm stuck, I can't really figure out how I can get the apic to accept interrupts from MSI/IO apic. I do understand that I have to fill the vector table of the io apic, but how can I get the APIC to accept interrupts from MSI AND the IO apic.

I hope some of you can push me in the correct direction!
Greets,
Bietje

Bietje wrote:Hey,

I have read some documents about the apic, io apic and msi. Also, I wrote some basic functions to write towards the apic, io apic + a function the read/write msi messages. I really want to build in MSI support since that is a quit clean method of building in PCI interrupt support.

But now I'm stuck, I can't really figure out how I can get the apic to accept interrupts from MSI/IO apic. I do understand that I have to fill the vector table of the io apic, but how can I get the APIC to accept interrupts from MSI AND the IO apic.

I hope some of you can push me in the correct direction!
Greets,
Bietje

This seems somewhat backwards. The MSI method of writing something to an address is probably the same method that the IO-APIC uses to signal interrupts to processor cores. You don't have to do anything in order for the processor to accept MSIs, other than programming the MSI PCI configuration space registers (to setup MSI), define interrupt handlers and enable interrupts / local APIC. Also, you do not read/write MSI messages yourself, it is the chipset / PCI device that does this when an MSI is dispatched as the device needs service. You can look in the AHCI specification for how MSI could be used & setup. AHCI allows for a rather complex MSI-setup with one MSI / interrupt number per port.