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ARMv8 announced
Posted: Thu Oct 27, 2011 5:42 pm
by OSwhatever
ARM has now announced ARMv8 which will include a 64-bit addressing mode.
Read more about it this presentation.
http://www.arm.com/files/downloads/ARMv ... ecture.pdf
Re: ARMv8 announced
Posted: Thu Oct 27, 2011 7:06 pm
by Coty
I just skimmed the presitation, but it looks like my hopes came true, it looks like it starts in 32bit mode and you set up 64bit or something like that... but that's cool because it means I won't HAVE to port my ARM project to get it to work with newer chips...
Re: ARMv8 announced
Posted: Thu Oct 27, 2011 11:46 pm
by thepowersgang
This looks very interesting. I have just managed to get an ARMv7 port of my OS booting, and the changes to the architecture between AArch32 and AArch64 look like they will make life simpler for us OSDevers.
That said, it does remind me of the x86/amd64 switch, except maybe a little neater. Congrats to ARM on this, and I look forward to seeing the hardware to develop for.
Re: ARMv8 announced
Posted: Fri Oct 28, 2011 5:25 am
by OSwhatever
One interesting feature here is that they have added support for 64KB as smallest page size and that way reduces the amount of page table levels. 2 level page table can address 4TB, 3 level page table can address 256TB.
Re: ARMv8 announced
Posted: Sat Oct 29, 2011 4:37 am
by ACcurrent
Finally a move away from intels' architecture. I only feel bad about it being patented and not open but Intels Arch was horrible anyway, especially their Itanium arch.
Re: ARMv8 announced
Posted: Mon Nov 07, 2011 11:35 am
by OSwhatever
ACcurrent wrote:Finally a move away from intels' architecture. I only feel bad about it being patented and not open but Intels Arch was horrible anyway, especially their Itanium arch.
What I've read about the Itanium and its ISA is that it is very extensive. It's a CPU packing with a lot of features and I can understand that it could be difficult to write a decent compiler for that CPU. Like many things from Intel they seems to just overcomplicate things.
I think there is still room for VLIW, especially in the embedded markets where performance/watt is an issue. If you look at Xtensa from Tensilica, they managed to make VLIW more attractive while also keeping the simplicity. One big VLIW instruction containing 3 (actually this is configurable) instructions that can be issued in parallel. These big instructions can also be mixed with the normal instructions. Having the compiler calculating parallelism isn't a bad thing and it shouldn't be too hard as long you don't clutter your ISA.