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Brendan wrote: for some CPUs the TSC doesn't run at a fixed frequency, but you can use the "thermal sensor" IRQ (in the local APIC) to determine when the speed of the RDTSC changes; and therefore you could still use the TSC for precise timing by doing something like "virtual_ticks += (current_TSC_count - last_TSC_count) * scaling_factor" (where the scaling factor is changed whenever the RDTSC speed changes).

limp wrote:Brendan mentioned to use the "thermal sensor" IRQ (in the local APIC) to determine when the speed of the RDTSC changes but I don’t really understand how this could be done in practice.

uint64_t virtual_ticks = 0;
uint64_t last_TSC_count = 0;
double scaling_factor = 1.0;

uint64_t get_virtual_ticks(void) {
    uint64_t current_TSC_count;

    current_TSC_count = RDTSC;
    virtual_ticks += (current_TSC_count - last_TSC_count) * scaling_factor;
    last_TSC_count = current_TSC_count;
    return virtual_ticks;
}

double scaling_factor_when_throttled = 0.5;

void thermal_status_IRQ(void) {

    // Update the virtual ticks counter first to account for time passed before the speed change

    get_virtual_ticks();

    // Set new scaling factor (for new speed)

    if( (getMSR(IA32_THERM_STATUS_MSR) & 1) == 0) {
        // Speed changed from "slow" to "normal"
        scaling_factor = 1.0;
    } else {
        // Speed changed from "normal" to "slow"
        scaling_factor = scaling_factor_when_throttled;
    }
}

    uint64_t start_time;
    uint64_t time_taken;

    start_time = get_virtual_ticks();
    do_something();
    time_taken = get_virtual_ticks() - start_time;

limp wrote:The problem I’ve got is that Intel manuals say that the aforementioned MSR has been introduced as an MSR in the 0x0F family, version 0x0 (i.e. Intel Xeon Processors).

Does that mean that my Intel Atom processor (family=0x6, model=0x1C) doesn’t support it? If not, how can I determine if a thermal event occurred in my case?

Brendan wrote: Some CPUs with "family = 6" are newer and do support it, and some CPUs with "family = 6" are older and don't support it. You have to look at the model number to determine which, um, "sub-family"(?) the CPU is.

Chronological order (for Intel) is "..., Pentium III (family 6), Pentium 4 (family F), Pentium M (family 6), ..., Sandy Bridge (family 6)".

limp wrote:According to my understanding, the only reason why the CPU frequency (and hence the TSC rate) should change is in the case that a thermal monitoring event forces it to change. So, if I ensure that no thermal events have happened during my measurements, I’ll assume that the CPU frequency (hence the TSC rate) was constant so the measurements accurate (no need to do mess with scaling factors etc.). Do you find something wrong to my assumption?

limp wrote:

Brendan wrote: Some CPUs with "family = 6" are newer and do support it, and some CPUs with "family = 6" are older and don't support it. You have to look at the model number to determine which, um, "sub-family"(?) the CPU is.

Chronological order (for Intel) is "..., Pentium III (family 6), Pentium 4 (family F), Pentium M (family 6), ..., Sandy Bridge (family 6)".

That’s really weird chronological order system Intel is using! As I said, my Intel Atom processor is family=0x6 and model=0x1C so I guess it’s newer than 0x0F family, version 0x0 which is where the IA32_THERM_STATUS MSR originally introduced. Is there an Intel document or something having a list of Intel’s CPUs family/models in chronological order?

limp wrote:One last thing that looked weird is that on the processor’s spec page, it is mentioned that it doesn’t support "Thermal Monitoring Technologies" however; the processor’s datasheet mentions that it supports TM1. What does Intel mean by “Thermal Monitoring Technologies”? Is this something else than TM1, TM2. By the way, I found using CPUID that both TM1 and TM2 are available on my processor.