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I'm reading the Intel 32/64 Architectures Software developers manual volume 3, Table 10-1 Local APIC Register Address Map.

It quite clearly gives the offset of each register, and says that all registers are 128 bit aligned, and 32,64 or 256bits in size,
and that all 32 bit registers should be accessed with aligned 32bit load/stores.

But only the ISR, TMR and IRR registers have their sizes documented.

What about the rest of them ?

Anyone know of any better LAPIC documentation ?

I'm trying to avoid just reading the linux kernel, or any other example code,
the copy/paste temptation if far too strong

THANKS.

cds84 wrote:I'm reading the Intel 32/64 Architectures Software developers manual volume 3, Table 10-1 Local APIC Register Address Map.

It quite clearly gives the offset of each register, and says that all registers are 128 bit aligned, and 32,64 or 256bits in size,
and that all 32 bit registers should be accessed with aligned 32bit load/stores.

But only the ISR, TMR and IRR registers have their sizes documented.
What about the rest of them ?
Anyone know of any better LAPIC documentation ?

It is all much simpler that you think. All APIC registers are 32-bit only.
The 64-bit registers are actually pair of two 32-bit registers (example ICR which is pair of ICR_LO and ICR_HI).
The registers that smaller than 32-bit are also 32-bit, but have extra bits ignored or reserved.
You can see all such registers with their fields pictures in the same manual later.

Stanislav

All registers are accessed via 32 bit access to locations which are aligned at 128 bit boundaries. If a register is wider than 32 bits, it is broken up into several non-contiguous 32 bit blocks, each of which is aligned at a 128 bit boundary. For example, the ISR (256 bits) has its lower 32 bits at address 0x100, the next 32 bits at 0x110 and so on (relative to the APIC base). The ICR (64 bits) occupies 32 bits at 0x300 and 32 bits at 0x310. If a register occupies only one 128 bit aligned address, it is 32 bits wide.