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Hi,
I'm working on building a basic sata driver. However I'm stuck trying to understand what the 'ports' are. I've been through the intel documentation several times. I have an intel ich9 chip-set, however Dell did not enable the standard 0x1f0-0x1f7 ports, so it's in I believe native Sata mode (no AHCI).
For accessing the disk and issuing FIS's do those go through the I/O ports which I've found with my PCI walk code in bars 1-4? Or do I have to memmap the registers, and if so how do I locate them? So are the bars the command and control for the phsyical sata ports 0/1? Or are they the SCR registers?

I'm hoping to just issue FIS PIO commands to the appropriate registers and avoid DMA for the moment.

Funny there was a reply here a minute ago?

Anyway my program interface does have bits 0/1 set it's value is 8f

And the BAR I/O ranges map as below, but when I try to issue standard ATA commands to them (just trying the identify drive command) BAR 0 and Bar 3 I get blank information back.

Device BAR # 0
Device base address FC10
Device upper address FC17
Device BAR # 1
Device base address FC08
Device upper address FC0B
Device BAR # 2
Device base address FC18
Device upper address FC1F
Device BAR # 3
Device base address FC0C
Device upper address FC0F
Device BAR # 4
Device base address FC20
Device upper address FC2F
Device BAR # 5
Device base address FC30
Device upper address FC3F

Here is my phantom post

I think FIS is an AHCI mode term. If you want to support native PCI IDE mode examine bit 0/2 (channel 1/2) of "Programming Interface Byte" (low-significant byte of class code). If this bit=1 you should use value of BAR0/2 as Command Block Base Address and value of BAR1/3 as Control Block Base Address (+2 for Device Control Register) for the channel 1/2. If the bit=0 you are in legacy mode and you should use 0x1F0-0x1F7/0x170-0x177 and 3F6h/376h IO ports for the channel 1/2.

Sorry, I have read about SATA native mode called DPA. In native PCI IDE mode BAR5 holds base address of SCR registers for the port 1 (+16 for the port 2 and so on). In DPA mode BAR0-1 holds 64-bit base address of MMIO SATA common registers (+200h for SATA port 1 registers, +400h for SATA port 2 registers and so on).

Could you post some of the information you were referencing? I can't find any documentation about how to work with DPA mode? The one intel doc I just found jives with what you said, but my BARs are showing up as I/O ports not memory mapped. So I don't know how you'd access 200h off of 0xfc18, because that's outside the reported range of the ports.

Sorry, I have the book in Russian. I can show the table with SATA registers (see below) but I don't know how to switch to DPA mode from native PCI IDE mode that you have.

I found the english version of the 31244 documentation, that's specifcially for the intel pciex - sata bridge chipset. The dell m610's use the ICh9 sata bridge.

I guess my question is given the chip is not in AHCI, and not in sub-native IDE mode (no 0x1f0-7 ports) I don't know what mode this is and how to talk to it, nor can I find any documentation. Is this DPA mode? because BAR5 is a port not mmio on mine so I don't think it applies.

As I can see you have native PCI IDE mode. An so you have access only to SCR registers through the I/O ports which base address is stored in BAR5.

K so saying it's in pci ide mode

the bars are I/o not memory locations

bar 0 = channel 0 command registers
bar 1 = channel 0 control regs
bar 2 = channel 1 command registers
bar 3 = channel 1 control regs
bar 4 = Dma regs
bar 5 = ata super set

So in my case to the 8 registers at FC10 - FC17 correspond to :
data
error
sectorcount
sector #
cyl low
cyl high
device
command/status

so that I could access them in PIO mode?

All right. Yes, you could.

except it doesn't respond to the identify drive command.

So the simple question is: can someone point me in the direction of how to transfer commands and data to this device?

My pci code can find the ports, but I cannot find how I issue command to them, what ports are and such. From that I've read FIS structures are for achi only, which this controller isn't configured for. So in native pci, how does one issue and receive commands/data?
The sata revision 2.6 spec doesn't help
The intel ich5 and 9 docs aren't much help either. At least for describing how to move data and in what format. Are task files the correct structure?