Another AMD issue with APIC timer / TSC?

[rdos]

I also have another issue, which is related to why I couldn't get more than 3 cores on my 4 core AMD Athlon to run. This issue seems to be related to hlt disabling APIC timer and/or TSC.

In order to get my OS to boot with 4 cores, I needed to change the null-loop like this:

Code: Select all

null_loop_start:
    GetApicId          ; gets the APIC ID into edx
    cmp edx,3

stopl:
    jz stopl             ; if it is core 3, do a busy loop
    
null_loop:
    hlt                   ; for other cores, do a hlt to save power
    jmp null_loop

If I remove the busy-loop on core 3, RDOS will hang early in the boot-process. When invoking the crash-debugger, it can be seen that core 0 has two threads ready to run, but they never become scheduled, probably because the timer never expires.

Anybody have an idea about this?

[Owen]

As you say TSC... CPUID 8000_0007.8?

TscInvariant. 1 = The TSC rate is ensured to be invariant across all P-States, C-States, and stop grant transitions (such as STPCLK Throttling); therefore the TSC is suitable for use as a source of time. 0 = No such guarantee is made and software should avoid attempt- ing to use the TSC as a source of time.

If 8000_0007 is not available, assume TSC is not monotonic