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I've been learning about memory segmentation on old processors for a while and I have a few questions.

On the 8086 (16 bit segment registers, 20 bit address bus), the only available mode was real mode and a selector:offset scheme was used. The selector pointed to the start of a segment and because the first four bits of the selector were blank, segments overlapped every 16 bytes, correct? Was the scheme supposed to be that they would always overlap or that they would only overlap if an application didn't need all of the space in its segment? Because if they always overlapped then two applications could be accessing the same location in memory which would cause problems, but from what I've read online it seems like there's a new segment every 16 bytes regardless of whether an application is using that memory.

On the 80286 (16 bit segment register, 24 bit address bus), a GDT was used in protected mode. The first 13 bits of the selector accessed an entry in the GDT, which contained a 24 bit linear address and the offset was added to that to find the correct memory address. If only the first 13 bytes of the selector are used to index the table, then the GDT can have a maximum of 2^13 entries which results in 2^13 addresses, which ruins the point of the 24 bit address bus. So how does the GDT allow access to all 2^24 memory addresses? I believe the 80386 uses the exact same system except for the modifications allowing 32 bits, so this question applies to that architecture as well.

Finally, paging seems very pointless if enough memory is available. It seems to me like it would nearly double the amount of RAM if it's used to its full extent (swap every page out, correct?), but if you're not using all of the RAM, the processor needs to process the page fault and resend the instruction even though you could have just mapped the linear address to the physical address without paging. So is paging always on or do operating systems control whether its on or off. And if its always on, why?

Thanks.

gsingh2011 wrote:I've been learning about memory segmentation on old processors for a while and I have a few questions.

On the 8086 (16 bit segment registers, 20 bit address bus), the only available mode was real mode and a selector:offset scheme was used. The selector pointed to the start of a segment and because the first four bits of the selector were blank, segments overlapped every 16 bytes, correct? Was the scheme supposed to be that they would always overlap or that they would only overlap if an application didn't need all of the space in its segment? Because if they always overlapped then two applications could be accessing the same location in memory which would cause problems, but from what I've read online it seems like there's a new segment every 16 bytes regardless of whether an application is using that memory.

65536 segments exist whether they're used or not, covering all multiples of 16. There is nothing to prevent different segments and addresses accessing the same byte, and no memory protection.

On the 80286 (16 bit segment register, 24 bit address bus), a GDT was used in protected mode. The first 13 bits of the selector accessed an entry in the GDT, which contained a 24 bit linear address and the offset was added to that to find the correct memory address. If only the first 13 bytes of the selector are used to index the table, then the GDT can have a maximum of 2^13 entries which results in 2^13 addresses, which ruins the point of the 24 bit address bus. So how does the GDT allow access to all 2^24 memory addresses? I believe the 80386 uses the exact same system except for the modifications allowing 32 bits, so this question applies to that architecture as well.

It only takes one GDT entry to access 4GB of memory. You don't need a different GDT entry to access each byte of memory.

Finally, paging seems very pointless if enough memory is available. It seems to me like it would nearly double the amount of RAM if it's used to its full extent (swap every page out, correct?), but if you're not using all of the RAM, the processor needs to process the page fault and resend the instruction even though you could have just mapped the linear address to the physical address without paging. So is paging always on or do operating systems control whether its on or off. And if its always on, why?

Paging is particularly useful in avoiding memory fragmentation. If you have a big file sitting in the middle memory and you need to load another big file into a space bigger than either of the free spaces in front of and after the first big file, without paging your only option is to move the first big file in order to create a big enough space to load the second one in, and it may not be possible to move it if the program using it has masses of variables pointing into it, many of which may be stored on a stack. With paging you can simply rearrange the two empty areas of memory to make them behave like a continuous block of memory which you can load the second file into, and the first file can be left alone. That's only one advantage of using paging, but it's enough to show that it isn't a waste of time.

Paging is initially switched off and your OS can leave it off if you like (mine currently doesn't switch it on at all). However, if you switch into 64-bit mode (on the PC - don't know about other processors), paging must be switched on, though you can set things up in such a way as to ignore it once you've created the necessary tables.

DavidCooper wrote:

On the 80286 (16 bit segment register, 24 bit address bus), a GDT was used in protected mode. The first 13 bits of the selector accessed an entry in the GDT, which contained a 24 bit linear address and the offset was added to that to find the correct memory address. If only the first 13 bytes of the selector are used to index the table, then the GDT can have a maximum of 2^13 entries which results in 2^13 addresses, which ruins the point of the 24 bit address bus. So how does the GDT allow access to all 2^24 memory addresses? I believe the 80386 uses the exact same system except for the modifications allowing 32 bits, so this question applies to that architecture as well.

It only takes one GDT entry to access 4GB of memory. You don't need a different GDT entry to access each byte of memory.

Only on the 386, not on 286. On 286, segments can only be 64k large, so in order to be able to access all 24 bits on the address bus, you need at least 256 GDT or LDT entries.