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whithin my code, i can't find any problem.
the following are the steps i used

1. A20 enble
2. PIC Init
3. Timer Setting
4. IDT Table mapping.

the code below is the code that i have used
--------------------------------------------------------------------------

#define IDTC_PRESENT 0x8000 /* group 1 */
#define IDTC_DPL0 0x0000 /* group 2 */
#define IDTC_DPL1 0x2000
#define IDTC_DPL2 0x4000
#define IDTC_DPL3 0x6000
#define IDTC_16BIT 0x0000 /* group 3 */
#define IDTC_32BIT 0x0800
#define IDTC_TASKGATE 0x0500 /* group 4 */
#define IDTC_INTGATE 0x0600
#define IDTC_TRAPGATE 0x0700

typedef struct _IDT_GATE {
WORD offset_low;
WORD selector;
WORD type;
WORD offset_high;
} IDT_GATE, *PIDT_GATE;

struct _DESC_TABLE_REG {
WORD size;
int address;
};
typedef struct _DESC_TABLE_REG IDTR_DESC;
typedef struct _DESC_TABLE_REG *PIDTR_DESC;

typedef struct _INT_HANDLER {
BYTE number;
int offset;
WORD type;
} INT_HANDLER, *PINT_HANDLER;

_declspec(naked) static void Handle_Fun(void)
{
{
static char *p = (PUCHAR)(0xb8000+158);
*p = 0x41;
    }

_asm {
inifite :
jmp inifite
}
}

#define MAX_IDT 256
static IDT_GATE m_IdtGate[MAX_IDT];
static IDTR_DESC m_IdtrDesc;
static INT_HANDLER m_IntHandlers[] = {
/* EXCEPTION HANDLER */
{ 0x00, (int)Handle_Fun,IDTC_PRESENT | IDTC_32BIT | IDTC_INTGATE | IDTC_DPL0 },
{ 0x01, (int)Handle_Fun,IDTC_PRESENT | IDTC_32BIT | IDTC_INTGATE | IDTC_DPL0 },
{ 0x02, (int)Handle_Fun,IDTC_PRESENT | IDTC_32BIT | IDTC_INTGATE | IDTC_DPL0 },
{ 0x03, (int)Handle_Fun,IDTC_PRESENT | IDTC_32BIT | IDTC_INTGATE | IDTC_DPL0 },
{ 0x04, (int)Handle_Fun,IDTC_PRESENT | IDTC_32BIT | IDTC_INTGATE | IDTC_DPL0 },
{ 0x05, (int)Handle_Fun,IDTC_PRESENT | IDTC_32BIT | IDTC_INTGATE | IDTC_DPL0 },
{ 0x06, (int)Handle_Fun,IDTC_PRESENT | IDTC_32BIT | IDTC_INTGATE | IDTC_DPL0 },
{ 0x07, (int)Handle_Fun,IDTC_PRESENT | IDTC_32BIT | IDTC_INTGATE | IDTC_DPL0 },
{ 0x08, (int)Handle_Fun,IDTC_PRESENT | IDTC_32BIT | IDTC_INTGATE | IDTC_DPL0 },
{ 0x09, (int)Handle_Fun,IDTC_PRESENT | IDTC_32BIT | IDTC_INTGATE | IDTC_DPL0 },
{ 0x0a, (int)Handle_Fun,IDTC_PRESENT | IDTC_32BIT | IDTC_INTGATE | IDTC_DPL0 },
{ 0x0b, (int)Handle_Fun,IDTC_PRESENT | IDTC_32BIT | IDTC_INTGATE | IDTC_DPL0 },
{ 0x0c, (int)Handle_Fun,IDTC_PRESENT | IDTC_32BIT | IDTC_INTGATE | IDTC_DPL0 },
{ 0x0d, (int)Handle_Fun,IDTC_PRESENT | IDTC_32BIT | IDTC_INTGATE | IDTC_DPL0 },
{ 0x0e, (int)Handle_Fun,IDTC_PRESENT | IDTC_32BIT | IDTC_INTGATE | IDTC_DPL0 },
{ 0x10, (int)Handle_Fun,IDTC_PRESENT | IDTC_32BIT | IDTC_INTGATE | IDTC_DPL0 },
{ 0x11, (int)Handle_Fun,IDTC_PRESENT | IDTC_32BIT | IDTC_INTGATE | IDTC_DPL0 },
{ 0x12, (int)Handle_Fun,IDTC_PRESENT | IDTC_32BIT | IDTC_INTGATE | IDTC_DPL0 },

///* IRQ HANDLER */
{ 0x21, (int)Handle_Fun,IDTC_PRESENT | IDTC_32BIT | IDTC_INTGATE | IDTC_DPL0 },
{ 0x22, (int)Handle_Fun,IDTC_PRESENT | IDTC_32BIT | IDTC_INTGATE | IDTC_DPL0 },
{ 0x23, (int)Handle_Fun,IDTC_PRESENT | IDTC_32BIT | IDTC_INTGATE | IDTC_DPL0 },
{ 0x24, (int)Handle_Fun,IDTC_PRESENT | IDTC_32BIT | IDTC_INTGATE | IDTC_DPL0 },
{ 0x25, (int)Handle_Fun,IDTC_PRESENT | IDTC_32BIT | IDTC_INTGATE | IDTC_DPL0 },
{ 0x26, (int)Handle_Fun,IDTC_PRESENT | IDTC_32BIT | IDTC_INTGATE | IDTC_DPL0 },
{ 0x27, (int)Handle_Fun,IDTC_PRESENT | IDTC_32BIT | IDTC_INTGATE | IDTC_DPL0 },
{ 0x28, (int)Handle_Fun,IDTC_PRESENT | IDTC_32BIT | IDTC_INTGATE | IDTC_DPL0 },
{ 0x29, (int)Handle_Fun,IDTC_PRESENT | IDTC_32BIT | IDTC_INTGATE | IDTC_DPL0 },
{ 0x2c, (int)Handle_Fun,IDTC_PRESENT | IDTC_32BIT | IDTC_INTGATE | IDTC_DPL0 },
{ 0x2d, (int)Handle_Fun,IDTC_PRESENT | IDTC_32BIT | IDTC_INTGATE | IDTC_DPL0 },
{ 0x2e, (int)Handle_Fun,IDTC_PRESENT | IDTC_32BIT | IDTC_INTGATE | IDTC_DPL0 },

/* TASK-GATE */
{ 0x20, (int)Handle_Fun,IDTC_PRESENT | IDTC_TASKGATE | IDTC_DPL0 },
{ 0x30, (int)Handle_Fun,IDTC_PRESENT | IDTC_TASKGATE | IDTC_DPL0 },

{0, 0, 0 }
};

int main(void)
{
UCHAR status, flag;
WORD timeout = (WORD)(1193180/50);
int i;

/* enable a20 */
do { status = READ_PORT_UCHAR((PUCHAR)0x64); } while( status & 0x02 );
WRITE_PORT_UCHAR((PUCHAR)0x64, 0xd0);
do { status = READ_PORT_UCHAR((PUCHAR)0x64); } while( !(status&0x01) );
flag = READ_PORT_UCHAR((PUCHAR)0x60);
flag |= 0x02;
do { status = READ_PORT_UCHAR((PUCHAR)0x64); } while( status & 0x02 );
WRITE_PORT_UCHAR((PUCHAR)0x64, 0xd1);
do { status = READ_PORT_UCHAR((PUCHAR)0x64); } while( status & 0x02 );
WRITE_PORT_UCHAR((PUCHAR)0x60, flag); /* write new flag */
do { status = READ_PORT_UCHAR((PUCHAR)0x64); } while( status & 0x02 );

/* PIC Init */
WRITE_PORT_UCHAR((PUCHAR)0x20, 0x11); /* edge trig, cascade mode, ICW4 */
WRITE_PORT_UCHAR((PUCHAR)0x21, 0x20); /* start at INT vector 20h */
WRITE_PORT_UCHAR((PUCHAR)0x21, 0x04); /* #IR2 pin has a slave */
WRITE_PORT_UCHAR((PUCHAR)0x21, 0x01); /* not sp, nonbuffered mode, normal EOI, for x86 */
WRITE_PORT_UCHAR((PUCHAR)0x21, 0x00);
WRITE_PORT_UCHAR((PUCHAR)0xa0, 0x11); /* edge trig, cascade mode, ICW4 */
WRITE_PORT_UCHAR((PUCHAR)0xa1, 0x28); /* start at INT vector 28h */
WRITE_PORT_UCHAR((PUCHAR)0xa1, 0x02); /* slave 8259 has been linked to master's #IR2 pin */
WRITE_PORT_UCHAR((PUCHAR)0xa1, 0x01); /* not sp, nonbuffered mode, normal EOI, for x86 */
WRITE_PORT_UCHAR((PUCHAR)0xa1, 0x00);

/* Timer Setting */
WRITE_PORT_UCHAR((PUCHAR)0x43, 0x34);
WRITE_PORT_UCHAR((PUCHAR)0x40, (UCHAR)(timeout & 0xff));
WRITE_PORT_UCHAR((PUCHAR)0x40, (UCHAR)(timeout >> );

memset(m_IdtGate, 0, MAX_IDT*sizeof(IDT_GATE));

/* make IDT table */
for(i=0; i<MAX_IDT; i++) {
if(m_IntHandlers[i].offset == 0)
break;

if((m_IntHandlers[i].type & IDTC_TASKGATE) == IDTC_TASKGATE) {
m_IdtGate[m_IntHandlers[i].number].selector = (WORD)(m_IntHandlers[i].offset);
m_IdtGate[m_IntHandlers[i].number].type = m_IntHandlers[i].type;
} else {
m_IdtGate[m_IntHandlers[i].number].selector = 0x0008;
m_IdtGate[m_IntHandlers[i].number].type = m_IntHandlers[i].type;
m_IdtGate[m_IntHandlers[i].number].offset_high = (WORD)(m_IntHandlers[i].offset >> 16);
m_IdtGate[m_IntHandlers[i].number].offset_low = (WORD)(m_IntHandlers[i].offset & 0xffff);
}
}

/* make IDTR vlue */
m_IdtrDesc.address = (int)&m_IdtGate;
m_IdtrDesc.size = (WORD)(MAX_IDT*sizeof(IDT_GATE));
HalpEnableInterrupt((PIDTR_DESC)&m_IdtrDesc);

_asm {
sti  // <<=================== Error........VMWARE reset..
}

CrtPrint("hi.........");
while(1);
return 0;
}

well, i'm tired too. when you know the error's place it's usually quite easy to find the problem. when the computer resets at "sti", theres a problem with the idt. the "sti" itself just checks, if the IO-privilege-level is equal to the current privilege level, or if the IOPL is 3. (it does not check the idtr yet!)
so, the error occours on the first interrupt coming. try debugging with bochs, think like the cpu and check all addresses. maybe you should also disassemble and see what you get

hi friend,

Where is your lidt ?  I mean you are supposed to load the idt register with the Interrupt table address. That I believe makes you reset after sti.

regards
Gandalf