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Hey guys, my plan is as follows...

To keep kernel purely 64bit, I switch to long mode in my stage 1.5.
Presently, i've been using 2meg pages. The first 2meg is identity mapped,
and the second physical page is mapped to the top 2gig of my virtual address space ( kernel runs here ).
This is all up and working fine.


To keep things simple in the early stages of my kernel startup, I would like to be able to access all of my physical memory at a constant virtual offset.

I have been trying to map a single 1 gig page at the top of my virtual address space ( for kernel )
and map a few 1 gig pages starting from virtual 0xffff800000000000 to physical 0x0000.
the idea here is that i will be able to access physical address X at virtual address (X + 0xffff800000000000)

The problem i am having, is that bochs crashes when i try to enable paging. complaining that only 32bit physical address is emulated, it gives a bogus physical address, and mentions the PDP ( PDP shouldn't be used in 1gig tables )

for now, I have disabled the kernel mapping, and im trying to get a single 1 gig page identity mapped to the first gigabyte of memory.

PML4E @ physical address 0x10000.
1st entry present, writeable, user, pt_write_through flags set.
points to physical address 0x11000 ( my PDPE )
PDPE @ physical address 0x11000
1st entry present, writeable, user, pt_write_through, global, TERMINAL flags set.
points to physical address 0x0000 ( identity mapped )

now time to enter long mode...

1) set PAE and PGE in cr4
2) load page PML4E (0x10000) to cr3
3) set bit 0x100 in mrs 0x80 to enable long mode
4) set bits 0x80000001 in cr0 to enable paging ant protection.
5) load GDT
6) long jump to long mode.

this crashes at stage 4) with bochs error, only 32bit physical addresses are emulated.

I have checked cpuid, and bochs supports 1gig pages.
EFER register is at value 0x500 ( LMA and LME bits set )

What else am i missing ?
AMD64 manual volume 2 says that a terminal bit in PDPE, with LMA and LME is enough to select 1 gig pages.

I am very confused :S

I must be missing something ? or doing something really stupid ?
Like i mentioned earlier, if i add a PDE, with a terminal flag, and clear PDPE terminal flag,
then my kernel boots, and runs fine with 2meg pages.

Very greatful for any prods in the right direction.
THANKS
Chris.

In CVS Bochs sources you have more verbose 'page' command.
If you type 'page LADDR' you will get translation for the page LADDR with all the details - what was the PML4 value, what was PDPE, PDE and PTE.
Also all page attributes are printed for convinience. Just stop in the debugger and you could easily see what went wrong in your paging.

You can also use 'trace-mem on' command to see all the memory accesses you actually execute including page walks.

now time to enter long mode...

1) set PAE and PGE in cr4
2) load page PML4E (0x10000) to cr3
3) set bit 0x100 in mrs 0x80 to enable long mode
4) set bits 0x80000001 in cr0 to enable paging ant protection.
5) load GDT
6) long jump to long mode.

this crashes at stage 4) with bochs error, only 32bit physical addresses are emulated.

BTW, EFER MSR is 0xc0000080 which is not really matching you step (3) ...

Stanislav

cds84 wrote: I must be missing something ? or doing something really stupid ?
Like i mentioned earlier, if i add a PDE, with a terminal flag, and clear PDPE terminal flag,
then my kernel boots, and runs fine with 2meg pages.

Very greatful for any prods in the right direction.
THANKS
Chris.

BTW, If you set the PS bit in the PDPE and 1G paging is not supported you will get the page fault exception.

P.S. Last Bochs 2.4.5 release already have no errors like "only 32-bit physical address supported". Which Bochs version you use ?
Did you try to update Bochs and see what happens ?

RESOLVED!

I was using gentoo stable bochs version ( 2.3.7 5 years old now ! )
I updated to the lastest testing version (2.4.5) as you recommended, and as if by magic, it started working as expected.

It turns out that even with 1gig pages supported ( in cpuid ) and the terminal flag set in PDPE, bochs was attempting to parse the contents of phyical address 0 as a PDE.
Which i believe contains the default IDT as set up by the bios.

Again, Thanks!