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Posted: **Thu Dec 02, 2010 7:11 am**

Dear guys,

I have a doubt in "The Global Descriptor Table", I am go throughing the tutorial written by "Jamesmolloy", which describes how to load GDT in kernel code. Please refer the below link for more information
http://www.jamesmolloy.co.uk/tutorial_h ... 20IDT.html

GDT loaded as below

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   gdt_set_gate(0, 0, 0, 0, 0);                // Null segment
   gdt_set_gate(1, 0, 0xFFFFFFFF, 0x9A, 0xCF); // Code segment
   gdt_set_gate(2, 0, 0xFFFFFFFF, 0x92, 0xCF); // Data segment
   gdt_set_gate(3, 0, 0xFFFFFFFF, 0xFA, 0xCF); // User mode code segment
   gdt_set_gate(4, 0, 0xFFFFFFFF, 0xF2, 0xCF); // User mode data segment

And he calls the ASM function "gdt_flush"

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[GLOBAL gdt_flush]    ; Allows the C code to call gdt_flush().

gdt_flush:
   mov eax, [esp+4]  ; Get the pointer to the GDT, passed as a parameter.
   lgdt [eax]        ; Load the new GDT pointer

   mov ax, 0x10      ; 0x10 is the offset in the GDT to our data segment
   mov ds, ax        ; Load all data segment selectors
   mov es, ax
   mov fs, ax
   mov gs, ax
   mov ss, ax
   jmp 0x08:.flush   ; 0x08 is the offset to our code segment: Far jump!
.flush:
   ret

In the above code, he is loading CS with 0x08, and other data segments with 0x10. The values 0x08 & 0x10 are GDT offset values for kernel code and data segments.

Here are my doubts:
1. Once the below code is executed, what the processor will understand?

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lgdt [lgdt_offset]        ; Load the new GDT pointer

2. Where the processor will store the GDT start address (or in which register) ?
3. Once we load the CS register with 0x08, whether it will look for the physical address 0x08 or the GDT offset at 0x08
4. In case, if CS register value always refers to one of the GDT entry (in SEGMENTED memory) then, in case of PAGE memory system how it will be?

Sorry if I have confused you.

Posted: **Thu Dec 02, 2010 8:45 am**

Hello,

When LGDT is executed, the processor obtains GDT base and limit from its operand and stores it in GDTR. This is always a physical address, and is where the start address of the GDT is stored for later use. (This addresses questions 1 and 2.)

Protected mode does not use segment registers as physical addresses (as addressed in questions 3 and 4.) It only contains a descriptor offset (... disregarding RPL bits) This is irrelevant if paging is used or not.

Posted: **Thu Dec 02, 2010 10:29 am**

neon wrote:When LGDT is executed, the processor obtains GDT base and limit from its operand and stores it in GDTR. This is always a physical address, and is where the start address of the GDT is stored for later use. (This addresses questions 1 and 2.)

Not true. LGDT is given the address of your GDTR in the virtual address space: first segmentation, then paging applies. The GDTR in turn contains the linear (not physical) address and the size of the GDT: when accessing the GDT later paging still applies if enabled, but not segmentation.

Technically, the only thing that happens when using LGDT, is that the contents of your GDTR in memory is copied to the processor's GDTR register.

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