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Hi guys,
I say it is very important because I would like to start writing today.
I know how to setup GDT, I also know in theory how to setu IDT. The thing I don't know is how use paging.
I have read a lot of texts, and some codes. The problem is what have paging to do with GDT?
At start I sets up some GDT entries for kernel CODE, DATA and STACK (+some more not very important). Now, what do I need to care about GDT when I enable paging.
When I have a GDT, and enable PAGING I must prepare first pages for the kernel, when the kernel's code descriptor base is 1MB and the limit 100(*granuality 4kb), and the actual kernel memory usage is 4kb*10, I sets 10 pages, and the rest of the mem will cause PF?, Is that right?
If no please send me some info.

Przemek Grzywacz

Thanks.

hi friend,

  To be honest paging has got nothing to do with GDT. Unless u set the "page enable" bit in cr0 u are safely out of #PF (page faults). However you will have to take care of memory management problems like external & internal fragmentations (coz without paging you are in segmented memory model).

And if u don't want to deal with external & internal fragmentations, then u must enable paging. For that part I believe the best will be to read Intel IA32 part 3(System Programmer) chapter 3 and 4.

As for Kernel page directory I believe 1-to-1 mapping works(hey guys got some other ideas - please let me know)

hope it helps.

rgds
Gandalf