IO APIC base

[lemonyii]

Hi again!
now my local APIC and 8259 works together smoothly in x86_64 mode.And i hope to get my IOAPIC to work.but i found it is so hard to get some practical information.i've searched here for long.
i read the MultiProcessorSpecificationV1.4. but i got only these:

The IMCR is supported by two read/writable or write-only I/O ports, 22h and 23h, which receive address and data respectively. To access the IMCR, write a value of 70h to I/O port 22h, which selects the IMCR. Then write the data to I/O port 23h. Writing a value of 01h forces the NMI and 8259 INTR signals to pass through the APIC.When the operating system is ready to switch to MP operation, it writes a 01H to the IMCR register, if that register is implemented, and enables I/O APIC Redirection Table entries. The hardware must not require any other action on the part of software to make the transition to Symmetric I/O mode.

so,does it mean these code will enable the IOAPIC and disable i8259 or do i have to do smth more?

Code: Select all

 mov   al,0x70
out   0x22,al
mov   al,0x01
out   0x23,al

then everything remain to do is to set the redirection table,right?
but the most cofusing thing i think is,

The default base address for the first I/O APIC is 0FEC0_0000h.Non-default APIC base addresses can be used if the MP configuration table is provided.

is there a fixed base address in x86(_64) or could i get the base address from a simple way? (say,not to search so much place for the stuctures metioned in MPSpecification?)
and where should i send the EOI ? to the local APIC or somewhere in IOAPIC? i can't find it.
i'm working on it.and i'll appreciate it if someone help me with these problems.
thx

[gerryg400]

The IMCR is supported by two read/writable or write-only I/O ports, 22h and 23h, which receive address and data respectively. To access the IMCR, write a value of 70h to I/O port 22h, which selects the IMCR. Then write the data to I/O port 23h. Writing a value of 01h forces the NMI and 8259 INTR signals to pass through the APIC.When the operating system is ready to switch to MP operation, it writes a 01H to the IMCR register, if that register is implemented, and enables I/O APIC Redirection Table entries. The hardware must not require any other action on the part of software to make the transition to Symmetric I/O mode.

You need to parse the MP config table to find out whether your machine has an IMCR register (bit7 of feature byte 2). None of my newer machines (even virtual machines) support PIC mode so there is no IMCR.
To switch to symmetric I/O mode I think all I did was initialise the 8259 with ALL intr lines masked and setup the IO apic redirection table. I can check later if you like.

is there a fixed base address in x86(_64) or could i get the base address from a simple way? (say,not to search so much place for the stuctures metioned in MPSpecification?)

You can probably assume the lapic address is 0xfec00000. That's a physical address so you need to map that into your kernel virtual space. You should search the MP config table to confirm it. You need to do that to find how many cores, type of I/O, busses etc. I'll check when I get back to my desk.

Good luck

- gerryg400

[xenos]

In an ACPI system, you can use the ACPI tables instead to find IOAPICs and their base addresses. Have a look an the section named "Multiple APIC Description Table" (MADT) in the current ACPI specification. It is quite similar to the MP tables, but there are some differences. For example, ACPI defines a continuous space of IRQ lines, while the MP tables use a different set of IRQ numbers for each bus. These tables will also tell you which IRQ line of the system is connected to which IOAPIC.

[lemonyii]

hi!
and it has been deep night in my country now.

all I did was initialise the 8259 with ALL intr lines masked and setup the IO apic redirection table.

i try to do these.but i still can't get my keyboard to work.this is part of my code i think matters:

Code: Select all

in the code initializing local apic:
	//set LINT0 to INTR
	sys_call(0ULL,_SYSCALL_LEVEL0,apic_write, 0x350ull, 0x700|INT_8259_IRQ0);
in ioapic initializing:
	outbyte(INT_M_CTL,	0x11);			// Master 8259, ICW1.
	outbyte(INT_S_CTL,	0x11);			// Slave  8259, ICW1.
	outbyte(INT_M_CTLMASK,	INT_8259_IRQ0);	// Master 8259, ICW2. 
	outbyte(INT_S_CTLMASK,	INT_8259_IRQ0+8);	// Slave  8259, ICW2.
	outbyte(INT_M_CTLMASK,	0x4);			// Master 8259, ICW3. 
	outbyte(INT_S_CTLMASK,	0x2);			// Slave  8259, ICW3.
	outbyte(INT_M_CTLMASK,	0x1);			// Master 8259, ICW4.
	outbyte(INT_S_CTLMASK,	0x1);			// Slave  8259, ICW4.
	outbyte(INT_M_CTLMASK,	0xFF);	// Master 8259, OCW1. mask all
	outbyte(INT_S_CTLMASK,	0xFF);	// Slave  8259, OCW1. mask all
	*((u32*)0xfec00000)=0x12;
	*((u32*)0xfec00010)=0x4100|INT_8259_IRQ0;  //this might be a problem,i think
	*((u32*)0xfec00000)=0x13;
	*((u32*)0xfec00010)=0;
in keyboard int handler:
	sys_call(0ULL,_SYSCALL_LEVEL0,apic_write,0xB0ull,0ull); //EOI

and now i get nothing happened in qemu,and even lost the apic timer interrupt in bochs.
do i missed smth or did wrong? and where should i send the EOI?

In an ACPI system, you can use the ACPI tables instead to find IOAPICs and their base addresses.

I think remember that i saw a message that many ACPI have problems,and that't why the "-noacpi" exsist in linux kernel startup option.(in fact,my new machine with AMD785G can't boot both fedora and suse without this).
is that right or has it been improved recent years?
thank you

[xenos]

and where should i send the EOI?

The EOI is always sent to the local APIC by writing 0 into APIC_BASE + 0xb0, see sec. 9.9.5 (Signaling Interrupt Service Completion) in the Intel docs, part 3A.

I think remember that i saw a message that many ACPI have problems,and that't why the "-noacpi" exsist in linux kernel startup option.(in fact,my new machine with AMD785G can't boot both fedora and suse without this).
is that right or has it been improved recent years?

In fact, I never had any problems with ACPI and Linux. At the moment I am using Ubuntu 9.10 with an ASUS M60J notebook with ACPI enabled and it works just fine. But I don't have that much experience with ACPI and how it evolved during the last years. I just discovered that the new version 4 of the ACPI spec has been released two weeks ago and I'm looking through it.

[lemonyii]

I just discovered that the new version 4 of the ACPI spec has been released two weeks ago and I'm looking through it.

i will try,too.but now i think the first thing i got to do is to get IOAPIC work, and i'm trying now.
thx

[hst]

hey could you share your code for the io apic initialization and how to parse the MP table.

[gerryg400]

hey could you share your code for the io apic initialization and how to parse the MP table.

This is a very old thread. There's no guarantee that the guys you are speaking to are still around. lemonyii in particular has been quiet for a while.

Anyway the wiki has good info including links to threads that will help. The multiprocessor spec is linked as well.

http://wiki.osdev.org/IOAPIC