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extern i64 APIC_init(){
	sys_call(0ULL,_SYSCALL_LEVEL0,init_apic);
	sys_call(1ULL,_SYSCALL_SET_INT,INT_VECTOR_IRQ0,_int_handler_timer,SYS_INT_HANDLER_TYPE_INT64,0ULL,0ULL);
	sys_call(0ULL,_SYSCALL_LEVEL0,set_apic_timer,0x8000,0xB0,0x00020000|INT_VECTOR_IRQ0);
	return 0;
}

bits 	64
align 	16
init_apic: 				
		pushf					
		cli
		push	rcx
		push	rsi
				
		mov  	rcx,1Bh    		
		rdmsr      				
		and  	rax,0xfffffffffffff000 
		mov  	rsi,rax    		
		mov		eax,0x000001FF	;0x000001FF -> 0xFFE000F0 - enable local APIC  and set spurious int vector to 0xFF
		mov  	[rsi+0xF0],eax   
		mov		eax,0xFFFFFFFF	;0xFFFFFFFF -> 0xFEE000E0 - set destination format register to flat model
		mov		[rsi+0xE0],eax	
		mov		eax,0x00000000	;0x00000000 -> 0xFEE00080 - set the task priority register to accept all interrupts
		mov		[rsi+0x80],eax	
		
		xor		rax,rax
		pop		rsi
		pop		rcx
		popf
		ret

align 	16
set_apic_timer:				;init_apic_timer(CR,DCR,LVT)
		;0x0000000B -> 0xFEE003E0 - set timer to divide by 1
		;0x00020040 -> 0xFEE00320 - enable timer, set periodic mode, set int vector to 0x40
		;0x00000064 -> 0xFEE00380 - set initial count to 100 (and make the timer start counting)
		pushf					
		cli
		push	rcx
		push	rsi
				
		mov  	rcx,1Bh    	
		rdmsr      		
		and  	rax,0xfffffffffffff000 
		mov  	rsi,rax    	
		pop		rax				;DCR
		mov		[rsi+0x3E0],eax
		mov		[rsi+0x320],edx ;LVT	
		mov		[rsi+0x380],edi	;CR
		
		xor		rax,rax
		pop		rcx
		popf
		ret

align 	16
_int_handler_timer:
		push	rcx
		push	rsi
		push	rax
		push	rdi
		
		mov  	rcx,1Bh    		
		rdmsr      				
		and  	rax,0xfffffffffffff000 
		mov  	rsi,rax    	
		;EOI
		xor		rax,rax		
		mov		[rsi+0xB0],eax
		;do something
		mov		rcx,80*200
		mov		rdi,0xb8000
		mov		rax,0x7244
		rep
		stosw

		pop		rdi
		pop		rax
		pop		rsi
		pop		rcx
		iretq

Code: Select all

%define LAPIC_timer_divisor        0x03E0
%define LAPIC_timer_vector         0x0320
%define LAPIC_timer_initial_count  0x0380


;void init_apic_timer(uint32_t CR, uint32_t DCR, uint32_t LVT)

;Input
; rsi    Local APIC timer divisor (0x0000000B = divide by 1)
; rdx    Local APIC timer LVT (0x00020040 = enable timer, set periodic mode, set int vector to 0x40)
; rdi    Local APIC timer initial count (0x00000064 = 100 ticks)

    align 16

set_apic_timer:            
    pushf                                   ;Save flags      
    cli                                     ;Disable IRQs earlier than necessary
    push rcx                                ;Save RCX
    push rsi                                ;Save Local APIC timer divisor

    mov rcx,1Bh                             ;rcx = model specific Local APIC base MSR
    rdmsr                                   ;edx:eax = model specific Local APIC base MSR (hopefully)
    and rax,0xfffffffffffff000              ;rax = 32-bit physical address of Local APIC (hopefully)
    mov rsi,rax                             ;rsi = 32-bit physical address of Local APIC (hopefully)
    pop rax                                 ;rax = Local APIC timer divisor
    mov [rsi+LAPIC_timer_divisor],eax       ;Set Local APIC timer divisor to value from input parameter that was in rsi
    mov [rsi+LAPIC_timer_vector],edx        ;Set Local APIC vector to the high 32-bits of the Local APIC base MSR
    mov [rsi+LAPIC_timer_initial_count],edi ;Set Local APIC initial count to value from input parameter that was in rdi

    xor rax,rax                             ;rax = zero, because the return value matters for functions that return "void"
    pop rcx                                 ;Restore RCX
    popf                                    ;Restore flags and (potentially) enable IRQs later than necessary
    ret

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align    16,db 0
tmp_gdt:
   .NULL   dd   0
         dd   0
   .D0:   DD   0FFFFH
         DD   0209200H
   .D1:   DD   0FFFFH
         DD   020B200H
   .D2:   DD   0FFFFH
         DD   020D200H
   .D3:   DD   0FFFFH
         DD   020F200H
   .C0:   dd   0FFFFH         
         DD   0AF9A00H      
   .C1:   dd   0FFFFH
         DD   0AFBA00H
   .C2:   dd   0FFFFH
         DD   0AFDA00H
   .C3:   dd   0FFFFH
         DD   0AFFA00H
   .TSS:   dd   0                        ;THIS WOULD BE INITIALIZED AT KERNEL INITIALING
         dd   0
         DD   0         ;base 63-32
         DD   0         ;Reserved

GDTLEN      EQU   $-tmp_gdt   
SegD0      equ tmp_gdt.D0-tmp_gdt
SegD1      equ tmp_gdt.D1-tmp_gdt
SegD2      equ tmp_gdt.D2-tmp_gdt
SegD3      equ tmp_gdt.D3-tmp_gdt
SegC0      equ   tmp_gdt.C0-tmp_gdt
SegC1      equ   tmp_gdt.C1-tmp_gdt
SegC2      equ   tmp_gdt.C2-tmp_gdt
SegC3      equ   tmp_gdt.C3-tmp_gdt
SelectorTSS equ tmp_gdt.TSS-tmp_gdt
GdtPtr:      dw   GDTLEN-1
         DD   0
         DD   0

;== TSS ==========================================      
align    16,db 0
tss:
   .reserved0   dd   0
   .rsp0      dd   0
            dd   0
   .rsp1      dd   0
            dd   0
   .rsp2      dd   0
            dd   0
   .reserved1   dd   0
   .reserved2   dd   0
   .ist1      dd   0
            dd   0
   .ist2      dd   0
            dd   0
   .ist3      dd   0
            dd   0
   .ist4      dd   0
            dd   0
   .ist5      dd   0
            dd   0
   .ist6      dd   0
            dd   0
   .ist7      dd   0
            dd   0
   .reserved3   dd   0
   .reserved4   dd   0
   .reserved5   DW   0
   .IOMapBase   dw   0xffff         ;somewhere invalid
   ;.IOMap      dd   0xffffffff      ;to ensure that it works well
   
TSSLEN      equ   $-tss

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    mov 	rcx,1Bh                         ;rcx = model specific Local APIC base MSR
    rdmsr                                   ;edx:eax = model specific Local APIC base MSR (hopefully)
	mov		rsi,rdx						;rsi = higher 32bit 
	shl		rsi,32
    and 	rax,0xfffffffffffff000           ;rax = lower 32-bit physical address of Local APIC (hopefully)
    mov 	esi,eax                           ;rsi = 64-bit physical address of Local APIC (hopefully)

Code: Select all

mov 	rcx,1Bh                         ;rcx = model specific Local APIC base MSR
rdmsr                                   ;edx:eax = model specific Local APIC base MSR (hopefully)
mov		rsi,rdx						;rsi = higher 32bit 
shl		rsi,32
and 	rax,0xfffffffffffff000           ;rax = lower 32-bit physical address of Local APIC (hopefully)
mov 	esi,eax                           ;rsi = 64(in fact 32)-bit physical address of Local APIC (hopefully)
pop 	rax                                 ;rax = Local APIC timer divisor
mov 	[rsi+LAPIC_timer_divisor],eax       ;Set Local APIC timer divisor to value from input parameter that was in rsi
mov 	[rsi+LAPIC_timer_vector],edx        ;Set Local APIC vector to the high 32-bits of the Local APIC base MSR
mov 	[rsi+LAPIC_timer_initial_count],edi ;Set Local APIC initial count to value from input parameter that was in rdi
mov		eax,esi			;eax =  apic base
mov		rcx,0x1B		;apic base MSR
wrmsr					;apic base MSR <- edx:eax

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; EDX has the right value set for the LVC timer register on input

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rdmsr                                      ;Rewrites EDX in the process of dumping the base MSR
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mov    [rsi+LAPIC_timer_vector],edx        ;Oops!
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