A coding case arose that I needed to far jump using a 64-bit offset. Checking the Intel instruction reference manual, I gladly found the far jump:
Code: Select all
REX.W + FF/5 JMP m16:64
But unfortunately, I found this under the far jumps section in the AMD instruction reference:
It may help to state that for testing purposes, I used two "REX.W far jump"s with 64-bit offsets. One in early kernel bootup code and one in the SMP trampoline. Code worked nicely on CVS Bochs and on my Intel Core2 hardware, but failed on qemu.Control is transferred to the target CS:rIP. In this case, the target offset can only be a 16 or 32 bit value, depending on operand-size, and is zero-extended to 64 bits.
I've been able to work around the 64-bit offset need; I'm wondering though, is this a real inconsistency, or a problem in my interpretations?
Thank you!