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Hi everybody,

I'm trying to write a 64bit (amd64) kernel. I want to switch to long mode by using a loader that is called by GRUB and jumps to the actual kernel loaded by GRUB as a module. In that loader I want to initialize the 64bit mode. Now I've just looked into the AMD64 Architecture Programmers Manual and I've realized that I need to set up paging before switching to long mode. My problem is that I want to keep the loader as small as possible (when I say 'small' I don't mean the size in bytes or so but the number of things I have to implement in the loader and not in the actual kernel) and therefore I'd like to initialize paging in the 64bit kernel and not in the loader. Is there any possibility to use something like a dummy paging structure (unlikely, I know) or a very short and simple implementation I can redefine later?

Thanks.

PS: Sorry if my English is a bit incomprehensible, I'm not a native speaker.
PPS: I hope this question is not too stupid, I just like to keep my code tidy.

Hi,

For long mode, you need paging - loading the PML4 is a part of the mode switch process. If you want to keep it really simple in the boot loader, you can define 1GiB pages, which at minimum will require 1xPML4 and 1xPDPT. You will also need to keep all your code in the same PML4E (gives you a huge area to work with, but if you want your loader low and your kernel high, this could be an issue, unless you add a second PDPT and map the same physical RAM twice - but that's getting more complex!).

Personally, I take the opposite view (although there's nothing wrong with how you want to do things). I try to keep as much of the "run once" boot time code out of the kernel and in the loader, where the memory can be recycled once the kernel has control.

Cheers,
Adam

Hi,

AJ wrote:For long mode, you need paging - loading the PML4 is a part of the mode switch process. If you want to keep it really simple in the boot loader, you can define 1GiB pages, which at minimum will require 1xPML4 and 1xPDPT. You will also need to keep all your code in the same PML4E (gives you a huge area to work with, but if you want your loader low and your kernel high, this could be an issue, unless you add a second PDPT and map the same physical RAM twice - but that's getting more complex!).

Unfortunately (as far as I know) the "1 GiB pages" option is only currently supported in the newest AMD CPUs; and even if it is supported it's probably a bad idea to use it for the first 1 GiB of RAM (e.g. from 0x00000000 to 0x3FFFFFFF) because this area uses many different types of caching (some areas are "write-back", some areas as "uncacheable", some areas are "write-protected", etc).


Cheers,

Brendan

Thanks for that - I had no idea as I've never tried 1GiB pages. Oh well - nice idea in theory.

Cheers,
Adam

Okay, thanks for your help! I think I'll set up a simple 4KB page table then in the loader.

Cheers,

jkrug