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hi what flags should have a page to be accessible to PL3. When I put for example 0x000b_8007 it gives me a GPF. It is present | Write | User (1 + 2 + 4). Do I need anything else? The PGT itself has flags of 7.

Your flags seem to be correct. The paging mechanism should generate a page fault if there was something wrong, not a GPF. Perhaps there is a problem with segmentation?

the user app:
CS = 0x23, AR = 0xFA
DS = SS = ES = FS = GS = 0x2B, AR = 0xF2

Cheers

That looks fine too... Intel's soft_dev_man vol. 3, chapter 5.12 lists a lot of possible reasons for a GPF. Maybe theres a caching problem (not probable, but if you exclude everything impossible, what remains has to be true, even if it's improbable).
Which instruction causes the GPF (just curious)?
BTW: I recommend to disable caching for video RAM as for any kind of memory mapped I/O. Set bit 4 (PCD) of the page table entry.

hey guess what! suddenly it all began to work. The PCD bit did not seem to change anything, but it also did not crash.

Thanks for support! Now I'm tracing why stack is walking (lol it eats my variable where I store cr3 so guess what happens: asm("mov %%ebx, %%cr3" : :"b" (_cr3) ))

Cheers,
Adrian.

incl ($0xb8010)     - possible, PGT 0 is supervisor only
incl ($0x8000_0000) - both the PGT and PGD is user accesible/writeable. this one used to cause gpf

Never use __asm__. Use __asm__ __volatile__ instead. I it's not true that GCC will optimize your code in __asm__, because it simply doesn't understand it.
When you use only __asm__, GCC will "optimize" your code by removing assembly block from output
You can even write
__asm__ __volatile__("foo %0\n\t"
"bar %1\n\t"
::"r"(test1),"r"(test2));

and GCC won't give any error.