TSS

[Adek336]

I have a tss segment defined, but ltr 0x18 gets a gpf. Could you send me some specs on the tss segment limit, flags and attribs?

Cheers,
Adrian

[Jarek Pelczar]

Look at Intel 80386 reference manual

[Chris Giese]

Here's my TSS code and data:


; 32-bit pmode code to set up TSS
; TSS address in descriptor is broken into two discontiguous 16-
; bit chunks, so you must set the address at run-time, like this:
mov eax,tss
mov [gdt_tss + 2],ax
shr eax,16
mov [gdt_tss + 4],al
mov [gdt_tss + 7],ah

; load task register with selector for TSS descriptor
mov ax,TSS_SEL
ltr ax
; ...
; ...

; here is the TSS:
tss:
dw 0, 0 ; back link
; store ring 0 ESP here before IRET to ring 3 code
tss_esp0:
dd 0 ; ESP0
dw KERNEL_DS, 0 ; SS0, reserved
dd 0 ; ESP1
dw 0, 0 ; SS1, reserved
dd 0 ; ESP2
dw 0, 0 ; SS2, reserved

dd 0 ; CR3
dd 0, 0 ; EIP, EFLAGS
dd 0, 0, 0, 0 ; EAX, ECX, EDX, EBX
dd 0, 0, 0, 0 ; ESP, EBP, ESI, EDI
dw 0, 0 ; ES, reserved
dw 0, 0 ; CS, reserved
dw 0, 0 ; SS, reserved
dw 0, 0 ; DS, reserved
dw 0, 0 ; FS, reserved
dw 0, 0 ; GS, reserved
dw 0, 0 ; LDT, reserved
dw 0, 104 ; debug, IO permission bitmap base
; ...
; ...

; here is the GDT
gdt:

; ...
; ...

; descriptor for TSS
TSS_SEL equ $-gdt
gdt_tss:
dw 103
dw 0
db 0
db 89h ; ring 0 available 32-bit TSS
db 0
db 0

[Adek336]

Thanx! I found the bug: ltr 0x18 instead ltr %ax (is ltr 0x18 treated like ltr (0x18)?)

Thanx,
Adrian.