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I've been having issues understanding the gdt layout according to Intel and AMD's manuals. I've seen plenty of protected mode examples that implement it and only one or two poorly documented ones that show how to write it for long mode. I have no troubles understanding what the individual bits do but the diagram throws me off a little as to how the bytes are ordered. Little-endian byte order makes some sense to me but it'd be simpler if someone could show me how to implement a gdt entry as a quad.

Start with the beginning. What do the manuals tell you? what did you learn from that? what exactly is it that you do not understand?
Just giving you yet another example isn't normally going to help when all the existing examples aren't helping you right now.

I understand what the base address is and what the individual options are such as code privledge level. I just can't tell from the diagram in the Intel manual which order those particular bytes are stored in memory. If x86 was Big-endian I wouldn't have an issue. If someone could show me a labeled snippet of code that lets understand byte-by-byte how my assembler (FASM) lays out that data structure I'd be eternally grateful. I realize I could use Brendan's example code for entering long mode but I'd prefer to understand bit by bit whats going on.

Have a look at fig. 4-20 and 4-21 in the AMD64 manual, part 2. They show the layout of code and data GDT entries.

Since x86 is little-endian, the byte ordering is from right to left and then from bottom to top, i.e. you start with the least significant byte first. So, byte by byte, the layout is as follows:

• Segment Limit 0-7
• Segment Limit 8-15
• Base Address 0-7
• Base Address 8-15
• Base Address 16-23
• Flage
• Segment Limit 16-19 + Flags
• Base Address 24-31

Most of them are ignored in long mode, anyway.

Thank you so much! That totally answered my question.