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Hey.

I've never actually done any DMA programming before, so sorry if this is a really stupid question (and it is). I know there's a DMA controller (which my reference calls the master DMA controller) and I know devices support DMA transfers (using the build-in DMA controller which my reference calls the secondary DMA controller, although I'm not sure if it's talking about the right thing). I read somewhere that this support for DMA transfers is unrelated to the DMA controller. Is this reference wrong? If not, I immagine that the DMA controller's job is to provide DMA support (sort of like a CPU replacement for transfers) for devices which don't have built-in DMA support.

Can anyone please clarify this?

There are two ways of doing DMA - using the legacy controller (like floppies and soundblaster chips do), or by using busmaster DMA.

What you are probably confusing is the fact that there are many DMA controllers in a modern system. Each one is able to claim the system bus and grant transfers for its associated set of devices. Moreover, the system is hierarchical. PCI devices send DMA requests over the PCI bus, which the PCI host controller changes into the required signaling to shut up the processor (and other potential DMA transfers). PCIe and AGP also have DMA capabilities. So do the pair of legacy DMA chips.

In ancient systems the legacy DMA chips were the only one to compete for the bus besides the CPU itself. ISA devices had wires running to these DMA chips in order to start transfers. Nowadays, ISA devices, PCI/AGP/PCIe devices, and integrated stuff can all request access to the system bus, which has to be guided in good direction so that they don't overlap. I expect that there be a "logical" master DMA controller somewhere in the chipset, which is daisychained to the other DMA-capable parts of the system (probably onboard the same chip).

Bottom line, Only ISA devices use the legacy DMA controller (the ones you need to program as "DMA controller") for PCI the DMA controller works mostly out of the box, for AGP you might want to do some background research on AGPGART. IOMMU is also a nice thing to google on.

Hope that explains things.

So I suspect for instance that on ISA buses, the DRQ floppy pin is connected with the DMA controller...