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64-Bit IDT - Triple Fault on Error
Posted: Thu Jan 22, 2009 4:08 am
by thepowersgang
I'm trying to get a 64-Bit IDT working on Bochs, but although I seem to have set the IDT up correctly when I do 'info idt' in the bochs debugger during my kernel's execution the IDT is parsed as a 32-Bit IDT.
Also when an interrupt / trap occurs the CPU triple faults instead of calling my handler.
Can anyone help me?
The addresses in the IDT (if it is parsed manually as a 64-bit one) are valid virtual addresses placed by a NASM macro.
<edit>
The RIP value that bochs gives on the triple fault is NOT in the interrupt handler, it's in the faulting code.
</edit>
Output of 'info idt 0 7'
Code: Select all
<bochs:4> info idt 0 7
Interrupt Descriptor Table (base=0xffff80000020e000, limit=4095):
IDT[0x00]=32-Bit Trap Gate target=0x0018:0x0020ae6f, DPL=0
IDT[0x01]=??? descriptor hi=0x00000000, lo=0xffff8000
IDT[0x02]=32-Bit Trap Gate target=0x0018:0x0020ae79, DPL=0
IDT[0x03]=??? descriptor hi=0x00000000, lo=0xffff8000
IDT[0x04]=32-Bit Trap Gate target=0x0018:0x0020ae83, DPL=0
IDT[0x05]=??? descriptor hi=0x00000000, lo=0xffff8000
IDT[0x06]=32-Bit Trap Gate target=0x0018:0x0020ae8d, DPL=0
IDT[0x07]=??? descriptor hi=0x00000000, lo=0xffff8000
Template IDT Entry (with base of 0)
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dd 0x00180000,0x00008F00,0x00000000,0x00000000
Re: 64-Bit IDT - Triple Fault on Error
Posted: Mon Jan 26, 2009 8:25 am
by thepowersgang
Sorry for the double post, but BUMP.
Re: 64-Bit IDT - Triple Fault on Error
Posted: Thu Jan 29, 2009 9:04 am
by thepowersgang
Not meaning to sound like a noob but: Please Help!!
I would prefer to be flamed than ignored.
Re: 64-Bit IDT - Triple Fault on Error
Posted: Thu Jan 29, 2009 12:34 pm
by nekros
FLAME! Are you sure you are even in long mode?
EDIT: Only noobs try to not sound like noobs.( No offense intended)
Re: 64-Bit IDT - Triple Fault on Error
Posted: Thu Jan 29, 2009 3:35 pm
by JohnnyTheDon
Did you do an STI? Do you have the PIC masked? Have you switched to long mode?
Just because bochs misinterprets your IDT in the debugger doesn't mean its doing the same during actual excecution. Another examble is info tab, which (in 2.3.7, not current CVS) doesn't show memory mapping above 4GB.
Re: 64-Bit IDT - Triple Fault on Error
Posted: Thu Jan 29, 2009 7:19 pm
by thepowersgang
I know I'm in long mode because I can execute 64-bit code properly. And at the moment I'm only trying to properly handle processor faults (Int 0-31). From the IDT dump in the debugger it seems that the correct address is used for the handlers but they do not seem to be being executed.
*Idea* Do you need a TSS in Long Mode even if you are still in kernel mode?
My Error handlers:
Code: Select all
%macro ISR_ERRNO 1
_Isr%1:
cli
push %1
jmp ErrorCommon
%endmacro
%macro ISR_NOERR 1
_Isr%1:
cli
push 0
push %1
jmp ErrorCommon
%endmacro
; ISR Definitions
ISR_NOERR 0; 0: Divide By Zero Exception
ISR_NOERR 1; 1: Debug Exception
ISR_NOERR 2; 2: Non Maskable Interrupt Exception
ISR_NOERR 3; 3: Int 3 Exception
ISR_NOERR 4; 4: INTO Exception
ISR_NOERR 5; 5: Out of Bounds Exception
ISR_NOERR 6; 6: Invalid Opcode Exception
ISR_NOERR 7; 7: Coprocessor Not Available Exception
ISR_ERRNO 8; 8: Double Fault Exception (With Error Code!)
ISR_NOERR 9; 9: Coprocessor Segment Overrun Exception
ISR_ERRNO 10; 10: Bad TSS Exception (With Error Code!)
ISR_ERRNO 11; 11: Segment Not Present Exception (With Error Code!)
ISR_ERRNO 12; 12: Stack Fault Exception (With Error Code!)
ISR_ERRNO 13; 13: General Protection Fault Exception (With Error Code!)
ISR_ERRNO 14; 14: Page Fault Exception (With Error Code!)
ISR_NOERR 15; 15: Reserved Exception
ISR_NOERR 16; 16: Floating Point Exception
ISR_NOERR 17; 17: Alignment Check Exception
ISR_NOERR 18; 18: Machine Check Exception
ISR_NOERR 19; 19: Reserved
ISR_NOERR 20; 20: Reserved
ISR_NOERR 21; 21: Reserved
ISR_NOERR 22; 22: Reserved
ISR_NOERR 23; 23: Reserved
ISR_NOERR 24; 24: Reserved
ISR_NOERR 25; 25: Reserved
ISR_NOERR 26; 26: Reserved
ISR_NOERR 27; 27: Reserved
ISR_NOERR 28; 28: Reserved
ISR_NOERR 29; 29: Reserved
ISR_NOERR 30; 30: Reserved
ISR_NOERR 31; 31: Reserved
; Macro Voodoo
%macro MPUSH 1-*
%rep %0
push %1
%rotate 1
%endrep
%endmacro
%macro MPOP 1-*
%rep %0
pop %1
%rotate 1
%endrep
%endmacro
%macro PUSHAQ 0
MPUSH rax, rcx, rdx, rbx
MPUSH rsp, rbp, rsi, rdi
MPUSH r8, r9, r10, r11
MPUSH r12, r13, r14, r15
%endmacro
%macro POPAQ 0
MPOP r15, r14, r13, r12
MPOP r11, r10, r9, r8
MPOP rdi, rsi, rbp, rsp
MPOP rbx, rdx, rcx, rax
%endmacro
%macro PUSHFPU 0
sub rsp, 512
FXSAVE [rsp]
%endmacro
%macro POPFPU 0
FXRSTOR [rsp]
add rsp, 512
%endmacro
; Common part of error handlers
ErrorCommon:
PUSHAQ
PUSHFPU
mov rdi, rsp
call _IDT_HandleError
POPFPU
POPAQ
add rsp, 16
iretq
Re: 64-Bit IDT - Triple Fault on Error
Posted: Thu Jan 29, 2009 8:11 pm
by JohnnyTheDon
*Idea* Do you need a TSS in Long Mode even if you are still in kernel mode?
Yes. I should've asked that...
The only field you need is RSP0 if you are using the normal stack switching mode, or one of the ISTs if you are using IST mode. I recommend just using RSP0 and no IST.
Re: 64-Bit IDT - Triple Fault on Error
Posted: Thu Jan 29, 2009 11:09 pm
by thepowersgang
Thanks, I think I can remember _something_ like that when I was reading the intel manuals but must have forgotten it.