OSDev.org

Hey guys, last week my professor in my Computer Architecture course was discussing caching and all it's benefits.

I've never really seen anything about caching and OS development together.

Is caching, such as L1 and L2, implemented by the hardware or does the programmer need to specifically use the caches? Can the programmer even touch the caches?

- The L1 and L2 caches are implemented in hardware (on the processor since the 486).
- The processor needs at some point be told to actually use the caches. Luckily the BIOS developers do that for you. Where the bios slacks off you can fix that yourself (like Writecombining for video memory)
- That means you have access to the cache controls. Physical access to the caches is difficult. Have a go at the intel manuals and look up:
a) PCD and PWT
b) MTRR
c) Page Attribute Table
d) CD and NW
e) Performance monitor
f) Debug registers
There are several opcodes that deal with cache management (CLFLUSH, INVLPG, (WB)INVD, Non-temporal stores)

Any questions?

Haha, plenty of questions!

Not sure if how much I'll actually get into the cache, I was just wondering since the way my professor presented caches, they seemed more of a behind-the-scenes, off-limits kind of thing.

To most programmers, the caches are indeed a behind-the-scenes thing. In the average case they'll just speed up things without requiring second thought.
Nevertheless there are cases when optimizing for having a cache can pay off greatly, which is the main reason you're being told about it.

There are a few CPU architectures that give you a lot more control over the cache. I'm too tired and no name comes to mind now.
Note that it's not necessarily a good thing, if it's software, it may be a better (or more fit) algorithm, but it's still software.

It hardly needs to be mentioned that caching in general is a common technique, one used in web browsers, disk drivers, and (in a modified form) virtual memory page management. The basic idea is that you can use a small amount of fast, local memory to reduce the number of times you need to fetch from some slower data source (a similar technique called memoization is used to avoid repeatedly computing data). The hardest parts in designing a caching system are determining optimal amount of cache memory, and deciding which data to retain and which to allow to drop out.

While a cache may be no more complex than a simple ring buffer, most caches are designed as hash tables or priority queues, with the key for a section of cached data being the some related information which is used to look it up (e.g., a memory page number, a URL, a disk sector number). As for CPU hardware caches are usually associative memories, for this reason. Most caching schemes are based on a Least Recently Used algorithm which tracks when the cached item was last used.

The same basic techniques are used on a larger scale in virtual memory systems, though the intent is in some ways the opposite of a cache.

Anyway, I'm veering off-topic towards theory, so I'll leave things at that.