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Hi, im sing the code neon corrected to go into protected. After i put some apic code referencing vector 1 - keyboard to generate a interrupt, and finally a isr who write on screen.
The code is without error but dont print on the screen. Any ideias?

bits 16
org 0x7c00

jmp main

main:

mov ax, word 0x0000
mov ds, ax

mov ax, word isr
mov [2008], word ax
mov [2010], word 0x8
mov [2012], word 1000111000000000b ; interrupt descriptor
mov [2014], word 0x0000

mov [2016], word 255
mov [2018], word 2000
mov [2020], word 0


mov [528], word 0xffff
mov [530], word 0x0000
mov [532], byte 0x00
mov [533], byte 0x9a
mov [534], byte 0xcf
mov [535], byte 0x00

mov [536], word 0xffff
mov [538], word 0x0000
mov [540], byte 0x00
mov [541], byte 0x92
mov [542], byte 0xcf
mov [543], byte 0x00

mov [1000], word 23
mov [1002], word 520
mov [1004], word 0x0000

cli
lgdt [1000]
mov eax,cr0
or al,0x01
mov cr0,eax

jmp 8:pm

jmp $

bits 32

pm:

mov ax, 8*2
mov ds,ax


lidt [2016]

mov eax, 0x12
mov [0xfec00000], dword eax
mov [0xfec00010], dword 0x00000001 ;apic

mov eax, 0x13
mov [0xfec00000], dword eax ;apic -
mov [0xfec00010], dword 0x00000000

jmp $

isr:

mov [0xb8000], byte 'A'
mov [0xb8001], byte 0x17

Neon also told you to rewrite that code. I can't read this, let alone figure what it does or is meant to do.

I hope that is not the complete code. If it is, it will triple fault when the ISR is called because you are not returning from it.

If this is a hardware interrupt, you need to enable interrupts first (STI instruction). Make sure you have mapped the PIT to a valid int handler first though.

Lastly, if this is a 1st stage boot loader, keep in mind that you are limited to 512 bytes. The assembler wont tell you, so if you go beyond 512 bytes you will run into problems.

hi, whats PIT?

http://www.catb.org/~esr/faqs/smart-questions.html
http://forum.osdev.org/viewtopic.php?f=1&t=16944

why i need to remap pit?
thanks

I think that was a typo - he meant PIC.

Cheers,
Adam

I think that was a typo - he meant PIC

You are right--I was thinking PIT (Because it uses IRQ 0), but you need to map the PIC. Thanks for the correction

why i need to remap pit?

If you want hardware exceptions enabled, and the PIC IRQ0 isnt mapped to use a valid IRQ handler defined by you, then almost as soon as you enable hardware interrupts, IRQ 0 will fire and execute invalid code.

Thus, you need to remap the PICs to use a valid base IRQ address in your IDT and define interrupt handlers for them. Search the Wiki or Google...there are alot of good info on the PIC.