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When I wrote the drivers for the RTL8139 and RTL8169 NIC chipsets, the BAR's reported from the PCI configuration space were IO addresses. Now that I'm getting ready to program for the Intel 82546eb chipset, I have ran into two issues dealing with BAR's. In the programming manual from Intel about the addressable spaces, it says that BAR0/1 are used for 32/64-bit MMIO address space and BAR2/4 are used for regular IO space. Unfortunately, the value reported for BAR0 is 0xD8020000 which is above my installed physical memory (1GB), thus rendering the given address invalid. I'm fairly positive I parsed the config space properly, but this value is just wrong. Should I be shifting the reported value to the right to compensate for the 4 flag bits? That value would seem more correct, but I havent read anything about that.

I'm incredibly tired and frustrated, so I'm off to bed, but in the AM I will post the BAR2 (IO) address value, and explain why it is wrong as well.

Also, the chipsets are running on the PCI-e bus (i think, they are integrated onto my Supermicro x7dva-e mobo), should I be parsing that bus instead, or is the pci bus responsible for reporting the BARs anyways?

I have very less knowledge in this subject. But, IMHO, what relation does the PCI configuration space entries have with the physical memory you have?

01000101 wrote:Unfortunately, the value reported for BAR0 is 0xD8020000 which is above my installed physical memory (1GB), thus rendering the given address invalid. (...) I'm incredibly tired and frustrated

I think it's the "incredibly tired" thing that got to you, given the fact that you normally seem knowledgable enough. The MMIO addresses of course have nothing to do with your physical memory. Indeed, be glad it's above it, so you don't loose anything :).


JAL

Let's pretend that was never posted.

01000101 wrote:Let's pretend that was never posted.

What's posted? Was there something posted? It must totally have escaped my attention, sorry :).


JAL