Page 1 of 1
ISR and IDT code stopped working when moved to AMD
Posted: Fri Aug 15, 2008 12:06 pm
by jaswax
I started out with my OS development on an intel 2.4GHZ P4 (old school CPU). When I was done with my PIC setup, IRS and IDT I had working code and I could catch and handle errors as well as hardware IRQ's.
I recently purchased a 2.5GHz Quad Core AMD (running Linux in 32 bit mode) and moved my development tools and code over to it. When I ran my code on the new hardware with QEMU it triple faulted before my OS caught it. I did some research and found that I may have a problem with way the PIC is setup and/or my IDT. I have read on AjSoft that I need to use APIC instead of PIC and that I need a 64bit IDT with 128 bit table entries even in 32 bit mode.
My questions are:
1. Is the information on AjSoft correct? and if so...
2. What is the structure of a 64 bit IDT?
3. Where can I get information on programming the APIC?
4. What happened to the PIC on AMD processors and why does it not work?
----------------------------------------------------------------------------------------------------
If the information on AjSoft is not correct then does anybody have any ideas on what may be wrong?
FYI: I do most of my programming in nasm.
Re: ISR and IDT code stopped working when moved to AMD
Posted: Fri Aug 15, 2008 1:25 pm
by inflater
1. Is the information on AjSoft correct? and if so...
I think that's stupid... you could run even DOS on your AMD... I run Patlock 0.0.1 (32-bit) on my 64-bit AMD and it works everywhere, if it's 486, too.
Re: ISR and IDT code stopped working when moved to AMD
Posted: Fri Aug 15, 2008 6:41 pm
by jaswax
I think that's stupid... you could run even DOS on your AMD... I run Patlock 0.0.1 (32-bit) on my 64-bit AMD and it works everywhere, if it's 486, too.
I thought it was stupid too! It should have legacy support and it does.
I found the problem:
After doing a little more research and debugging I found that I had an ISR disabled that was needed. It was needing to execute the ISR for IRQ 7. On the P4 it was ok for it to be disabled. Apparently on this AMD it is needed. Not sure what it is yet. Documents that I have read state that IRQ 7 is for a LPT port but I am not doing anything related to that. If anyone knows what IRQ 7 is please feel free to let me know.
Otherwise the problem is solved.
Thanks for the help.
Re: ISR and IDT code stopped working when moved to AMD
Posted: Sat Aug 16, 2008 12:27 am
by xyzzy
IRQ7 on the master PIC and IRQ15 on the slave PIC can be spurious IRQs. Upon receiving an IRQ, you should check if it is spurious, and if so, don't ACK it. This is my code to check:
Code: Select all
/* Check for spurious IRQs */
if(irq == 7) {
/* Read the in service register, check the high bit */
out8(0x23, 3);
if((in8(0x20) & 0x80) == 0) {
kprintf(LOG_DEBUG, "intr: spurious IRQ7 (master), ignoring...\n");
return false;
}
} else if(irq == 15) {
/* Read the in service register, check the high bit */
out8(0xA3, 3);
if((in8(0xA0) & 0x80) == 0) {
kprintf(LOG_DEBUG, "intr: spurious IRQ15 (slave), ignoring...\n");
return false;
}
}
Re: ISR and IDT code stopped working when moved to AMD
Posted: Sun Aug 17, 2008 10:52 am
by AJ
jaswax wrote: I have read on AjSoft that I need to use APIC instead of PIC and that I need a 64bit IDT with 128 bit table entries even in 32 bit mode.
Erm - I wrote the entire site and there are no practical tutorials on there (just some basic design advice). If it really says either of those things, I would be very grateful to know where they are so I can correct them. The best I can think of where you got this from is:
1) The APIC: I advise using this where it is present and using the APIC timer instead of the PIT fo scheduling to allow a separate scheduling interrupt per core.
2) I mention that you need the Long Mode IDT even in
32 bit Compatibility Mode (not in 32 bit
protected mode).
Even though I have only just written the site, communicating either of the ideas you have picked up would certainly not have been intentional.
Cheers,
Adam
Re: ISR and IDT code stopped working when moved to AMD
Posted: Sun Aug 17, 2008 1:19 pm
by jaswax
@AJ - I suspected that was your website. The eyes gave it away! In any case I had just misread it. Sorry for that. I was upset when I discovered that my code that just worked on a P4 would not work on an AMD so I was not really thinking straight. I did a Google search on "triple fault after enabling interrupts" and it took me right to your site.
It would be nice to locate tutorial(s) on programming an APIC and IO APIC. Any ideas on where I could find one? One of these days I am going to want to do that!
Re: ISR and IDT code stopped working when moved to AMD
Posted: Mon Aug 18, 2008 12:24 pm
by AJ
Hi,
I got started with
Bona Fide OS Dev where there is an article on the APIC and one on SMP. I believe that the best way to get the full spec for the APIC is via the Intel Manuals, though.
Good to know I wasn't completely asleep when writing my site then - was worried there for a bit!
Cheers,
Adam