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APIC registers are 64-bits. I'm trying to read them on a 32-bit machine.

I first tried to let gcc deal with "unsigned long long" types, but the generated code does 2 32-bits reads. Say I want to read register at addres A, the code reads 32 bits at A and 32 bits at A+4, which is invalid for reading an APIC register (misaligned read).

So I tried to read with the "movq" instruction, but bochs gives an error "read spans 32-bits boundary" (sic).

So, must I assume that only the lower 32-bits of each APIC register can be read on a 32-bits machine ?

LAPIC has 32 bit regs.

IOAPIC has 64bit regs which are accessed using 32bit read/writes.
you write dword to fec00000h (write 10h for low 32bits, or 11h for high 32bits of 1st entry) then you read/write data(low/high 32bits of the redirection entry) from fec00010h(IOWIN).

any other APIC?

Ok, mine is a LAPIC. I must have misread that part in the Intel manual.

Thanks for the tip.

LocalAPIC: "Wider register (64bit or 128bit) should be accessed using multiple 32bit loads...", Section 8.4.1 after figure 8.4("Local APIC Structure")
I never had to deal with TMR,ISR,IRR I think they are for lapic.