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a question on makefile
Posted: Tue Feb 26, 2008 4:56 am
by crasher
In linux kernel source tree, most of directories have a makefile each.
Some of them have only serveral lines like
Code: Select all
subdir-y += video
obj-y += font_8x14.o
obj-y += font_8x16.o
obj-y += font_8x8.o
obj-y += vga.o
Could someone tell me how this obj-y is compiled without a $(CC) command being used?
Posted: Tue Feb 26, 2008 5:25 am
by JamesM
The low-level makefiles can't compile by themselves. try going into that directory and typing 'make'. It won't work.
They're included by the top level makefile. Look there.
Posted: Tue Feb 26, 2008 7:33 am
by Solar
@ crasher:
That subdir makefile is extending the list of subdirectories and object files that is maintained by the top-level directory. Personally, I prefer a single top-level Makefile using shell find to do that for me so I don't have to maintain more than one Makefile, or register added sources somehow.
Your way has the advantage of ignoring any temporary source files you might have floating around, though.
Posted: Tue Feb 26, 2008 9:22 am
by JamesM
I prefer a mix between the two. I use one top-level makefile which builds the bootloader, kernel, modules, userspace libraries etc. Each major component (the kernel, bootloader, each module etc) has its own makefile which specifies the directory tree and sources. That way one can have temporary files hanging around and also all the sources are specified in one place.
Posted: Tue Feb 26, 2008 8:02 pm
by crasher
In the toplevel rules.mk, I found a statement "include makefile". I cannot figure out how "make" find the full path to the objects since each sub-dir makefile only specifies the object name. The attached is the zip file of toplevel makefile & rules.mk and subdir makefile & rules.mk. They are taken out from the xen-3.1.0 source tar ball.