OSDev.org

Posted: **Wed Feb 20, 2008 6:55 pm**

I'm having a little trouble with the PML4. I seem to be unable to RTFM an GTFI on the PML4. Can someone point me to some kind info on setting PML4 up?

PS. I STFW

Posted: **Wed Feb 20, 2008 8:33 pm**

Sounds like you are not familiar with paging at all. Then any Protected Mode tutorial will be good for you.

Anyway, since you are hacker you should understand assembly at least a little

Code: Select all

use32
PMode32:
  mov  eax, data_selector      ;load 4GB data descriptor
  xor  ecx, ecx
  mov  ds, ax             ;to almost all segment registers
  mov  es, ax
  mov  ss, ax
  mov  fs, cx
  mov  gs, cx

  mov  eax, cr4
  or   eax, 1 shl 5
  mov  cr4, eax           ;enable PAE

  ;clear all 4 tables(PML4,PDP,PD,PT)
  xor  eax, eax
  mov  edi, 100000h
  mov  ecx, 512*8         ;512 entries in one table
  rep  stosd              ;write dwords

  ;PML4 located at 100000h
  ;PDP  located at 101000h
  ;Page-Directory at 102000h
  ;Page-table not required since we map 2MB pages

  mov  dword [100000h], 101000h + 111b          ;1st PML4 Entry points to PDP table
  mov  dword [101000h], 102000h + 111b          ;1st PDP Entry points to PD table
  mov  dword [102000h+8*0], 0h + 110000111b      ;1st PD Entry points to 0MB
  mov  dword [102000h+8*1], 200000h + 110000011b ;2nd PD Entry points to 2MB 
  mov  dword [102000h+8*2], 400000h + 110000011b ;3rd PD Entry points to 4MB 

  ;          addr + entry #   memory(page)     permissions
  mov  dword [102000h+8*3],   600000h      +   110000011b


  mov  eax, 100000h
  mov  cr3, eax           ;load PML4 base
  mov  ecx, 0C0000080h    ;EFER MSR
  rdmsr
  or   eax, 1 shl 8       ;enable long mode
  wrmsr
  mov  eax, cr0
  or   eax, 1 shl 31      ;enable paging
  mov  cr0, eax

  jmp  code64_selector:LongMode                                            

use64
LongMode:

Posted: **Wed Feb 20, 2008 8:40 pm**

In fact I'm writing my entire kernel in asm.

Thanks!

Posted: **Thu Feb 21, 2008 4:52 pm**

I'm still a little confused here though as your code uses actual numerical addresses to setup paging.

Posted: **Thu Feb 21, 2008 5:57 pm**

The entire paging method is described in the intel manual. Assuming that you have indeed RTFMed, what do you not understand about it?

Posted: **Fri Feb 22, 2008 12:10 am**

os.hacker64 wrote: Can someone point me to some kind info on setting PML4 up?
PS. I STFW

I doubt such tutorial exists simply because pml4 follows same rules as other tables.

Like combuster said be specific in your questions.
I mapped physical & virtual spaces as 1 to 1 (virtual mem addr corresponds to same physical addr). Code written using Fasm syntax. Processor(in its mind) will clear permissions(flags) bits when its time to use the page. Each entry in any table is 8 baits.

Posted: **Fri Feb 22, 2008 2:48 am**

Hi,

I set my 64 bit paging up using a combination of my existing 32 bit paging functions and this page.

Cheers,
Adam

Posted: **Fri Feb 22, 2008 11:05 am**

When I get back from school I'll explain paging here for myself, I hope you can find some errors...

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