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Well, it will be series of questions pertaining to my design of OS.
I decided to use PIO for Hard Disk and that too for ATA.I am confused about these :
1. IBM int13H Extensions use 32bit LBA Address while using 1F0 and 1F8 port addresses i can use 28bit LBA Address only, is there any other specification of ATA.

2. After doing PIO with Hard disk I have to remain in tight loop for checking the status of the controller. Is there any way that controller informs me about its status i.e. Interrupt Driven IO.

Pitchu wrote:Well, it will be series of questions pertaining to my design of OS.
I decided to use PIO for Hard Disk and that too for ATA.I am confused about these :
1. IBM int13H Extensions use 32bit LBA Address while using 1F0 and 1F8 port addresses i can use 28bit LBA Address only, is there any other specification of ATA.

2. After doing PIO with Hard disk I have to remain in tight loop for checking the status of the controller. Is there any way that controller informs me about its status i.e. Interrupt Driven IO.

int 13h Extensions use 64bit LBA and modern hard disks use 48bit lba
I suggest to write directly a hd dma driver instead of a hd pio driver
is a litle more work but the performance is many times better.
You can find the docs in t13.org

int 13h Extensions use 64bit LBA and modern hard disks use 48bit lba

Yep, U r correct it is as we can access 2^64 sectors in IBM int13h and that i mentioned 32bit address was because i had read about it long ago.
Thanks for info about modern hard disks(48 bit) and link for hd dma.
But the problem is that if i have to do PIO im limited to 28 bit LBA address on ATA-1, what if its capacity is more than that?How to access it using PIO.
One more thing is there any mechanism that i am interrupted after completion of Transfer.....I dont remember i think its Cascaded IRQ14 that is fired.

Pitchu wrote:

int 13h Extensions use 64bit LBA and modern hard disks use 48bit lba

Yep, U r correct it is as we can access 2^64 sectors in IBM int13h and that i mentioned 32bit address was because i had read about it long ago.
Thanks for info about modern hard disks(48 bit) and link for hd dma.
But the problem is that if i have to do PIO im limited to 28 bit LBA address on ATA-1, what if its capacity is more than that?How to access it using PIO.
One more thing is there any mechanism that i am interrupted after completion of Transfer.....I dont remember i think its Cascaded IRQ14 that is fired.

You can also do a PIO driver using 48bit lba read ATA-5 specs
if you understand assembly,on my OS i have PIO and DMA drivers that use
lba28 and lba48.
If you use PIO there is a interrupt when you can start the transfer,but only if the port becomes busy,and after the transfer is complete.
with DMA there is a interrupt after transfer completion.
If you want something simple use PIO without interrupts but polling the
status port.

This is what I used for my LBA28 driver

--Michael

octavio wrote:int 13h Extensions use 64bit LBA and modern hard disks use 48bit lba
I suggest to write directly a hd dma driver instead of a hd pio driver
is a litle more work but the performance is many times better.
You can find the docs in t13.org

Isn't supposed that the legacy DMA chips would be very slow at transfers compared to the I/O functionality of fast computers?

I have heard something like "8237 DMA chips work at a low frequency which doesn't provide an important improvement for reading/writing hard disks. The ideal would be to use Bus Master/Ultra DMA, also known as the hard disk's DMA using another chip-set, which unfortunately is programmed differently for every vendor's chipsets and models".

Also does anybody know the frequency at which the 8237 DMA controllers work at?

4 MB/second but more like 500 KB/second due to ISA bus protocols? Maybe PIO is faster than that?

It would be better if somebody could clarify that.

t0xic wrote:This is what I used for my LBA28 driver

--Michael

Wow... that makes it looks REALLY easy!

-Rich

Yea. Just make sure that you do it all right the first time I tried that code around 6 months ago and couldn't get it to work, but then implemented it in 10 minutes a few nights ago.

--Michael

~ wrote:
I have heard something like "8237 DMA chips work at a low frequency which doesn't provide an important improvement for reading/writing hard disks. The ideal would be to use Bus Master/Ultra DMA, also known as the hard disk's DMA using another chip-set, which unfortunately is programmed differently for every vendor's chipsets and models".
.

when i say 'DMA' i'm not talking about 8237 dma chips but about pci bus master or ultra dma.
The dma setup can be different for every vendor's chipset but the ultra
dma driver is standard.
And the dma setup is done by bios, udma driver don't care about wich dma mode it is using.

If you use PIO there is a interrupt when you can start the transfer,but only if the port becomes busy,and after the transfer is complete.

Sorry Pal I wasnt able to get u. Would u like to put it more clearly...

Pitchu wrote:

If you use PIO there is a interrupt when you can start the transfer,but only if the port becomes busy,and after the transfer is complete.

Sorry Pal I wasnt able to get u. Would u like to put it more clearly...

if busy bit of status port is not set then there not will be any irq ,this can happens if the contreler is ready for the data transfer.
in other words : only wait for a irq if the busy bit is set.

Ok I think i got u.
After sending the command for data transfer I will check for busy bit.
If it is not set then tranfer is going on else if it is set IRQ fires when transfer takes place.
Hope I got it and if so is it the same IRQ14 that gets fired.
If not then do tell me which IRQ as its corresponding index in IDT will be used to do house keeping.