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Scheduling and DPL0 stack
Posted: Wed Jan 09, 2008 4:34 am
by XCHG
I'm rewriting my scheduler. I've forgotten if I'm right about this or not. Suppose there are two DPL0 tasks running at the given moment. When IRQ0 is fired, are these the registers that are pushed onto the stack?
1) EFLAGS
2) CS
3) EIP
And for DPL3 to DPL0:
1) SS
2) ESP
3) EFLAGS
4) CS
5) EIP
Could somebody please confirm or correct this?
Posted: Wed Jan 09, 2008 5:12 am
by JamesM
yes, but I'm not certain about the order. Check the intel manuals. (volume 2.1: instruction 'INT')
Posted: Wed Jan 09, 2008 10:08 am
by JAAman
JamesM wrote:yes, but I'm not certain about the order. Check the intel manuals. (volume 2.1: instruction 'INT')
better section would be: 3A:5.12.1 (and figure 5-4 in same section)
this section does a better and simpler job of explaining exactly how the stack is used in these situations... from an OSdevers POV
Posted: Wed Jan 09, 2008 3:30 pm
by bewing
You have all the orders correct. EIP is always the value at the very bottom of the stack after any INT. SS and ESP are put on the stack before the EIP/CS/EFLAGS.