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dose anyone know of any long mode paging tutorials because apparently it is different form normal pagging

Why do you need a tutorial? Read through the Intel docs. There are a few extra bits you need to set (IIRC when I last read the section on paging) and I think you may be forced to use 4MB pages? But, it all should be explained in detail in the Intel doc and it shouldn't be too different if you understand x86 paging.

Uh... Intel has long mode? I haven't seen a 64-bit intel CPU on the shelf yet.

AMD's been out with them for the last two years at the very least. I'd stick with AMD's instruction set if they differ at all, since anyone with 64-bit is using that.

I too am interested in reading a tutorial. 800 page PDF docs are for people who want to spend 6 months studying to write a 40 instruction sequence. I prefer to just get the layman's version, thanks.

Sincerely,
the Devil

Avarok wrote:Uh... Intel has long mode? I haven't seen a 64-bit intel CPU on the shelf yet.

Intel did try going in a different direction with their 64bit Itanium architecture, but they eventually decided to incorporate AMD's 64bit x86 enhancements.

http://en.wikipedia.org/wiki/X86_64#History_of_Intel_64

Many OS's still call their port "amd64", but they often support Intel processors anyway..

Hi,

Avarok wrote:Uh... Intel has long mode? I haven't seen a 64-bit intel CPU on the shelf yet.

AMD's been out with them for the last two years at the very least. I'd stick with AMD's instruction set if they differ at all, since anyone with 64-bit is using that.

Intel have supported 64-bit/long mode for ages (introduced in 2004, but possbly not widely available until 2005). It's almost identical to AMD's long mode (there's always minor differences between CPUs, even CPUs made by the same manufacturer).

For long mode, paging is very similar to a 32-bit CPUs using PAE. Pages are 4 KB (but you can use "large pages" that are 2 MB, and a mixture of 4 KB and 2 MB pages in the same address space).

There's also more levels to the paging structures - the page tables and page directory are identical to 32-bit paging with PAE, the "page directory pointer table" has been enlarged to 4 KB (for 32-bit paging with PAE it's only 4 entries or 32 bytes). On top of this they added a new table (the "Page Map Level 4"). CR3 contains the physical address of the PLM4, which contains physical addresses for page directory pointer tables, which contains addresses for page directories, which contains addresses for page tables (for 4KB pages) and/or addresses for large pages.

Also, AMD added the "NX" (No-eXecute) bit, and back-ported it to 32-bit PAE (e.g. a 32-bit OS that uses PAE can use the no-execute feature if it's running on a 64-bit CPU). This is another page protection flag (like the read/write page protection flags) that allows the OS to make it impossible for page/s (e.g. data, stack) to be executed. Intel have this too, but they call it the "XD" (eXecute Disable) bit.

Mostly, it's the exact same principles that 80x86 CPUs have been using for 20 years, that have been extended (with more paging structures) to make it work for a larger linear address space size. The same flags have the same meanings as they did for 32-bit CPUs (G, PAT, D, A, PCD, PWT, U/S, R/W, P), and things like TLB invalidation are identical.

Lastly, AMD have recently added "1 GB page" support. I'm not sure if this has reached the shelves yet, but from it's name it's easy to guess how it works - entries in the PLM4 may point to a huge page of RAM instead of pointing to a page directory (just like 2 MB pages, where page directory entries may point to a large page of RAM instead of pointing to a page table).


Cheers,

Brendan

Not sure about tutorial ..., once you know protected mode - long mode is simple. Paging maybe most puzzling.
Extremely simple and commented sources: http://flatassembler.net/examples.php
related thread http://board.flatassembler.net/topic.php?t=6206
+ intel manuals, once you see something in sources you press 'search' button for this thing in PDF file.

Avarok wrote:I too am interested in reading a tutorial. 800 page PDF docs are for people who want to spend 6 months studying to write a 40 instruction sequence. I prefer to just get the layman's version, thanks.

They also deliver hard copies for free (as mentioned 100+ times on this forum).

Let's see if I can't figure this out..
- Open Volume 3A - System Programming Guide Part 2
- Scan contents: Protected-mode-memory management>Pae-enabled paging in IA-32e mode
- Turn to page 3-37

Okay, the following few pages (text + diagrams) show the exactly layout of the page directory and page table structures in memory, and step by step instructions. If you need a tutorial to work out that, then I'm afraid you won't get very far when one day you try to implement an ISO 9660 driver, or a network card driver with nothing more than a few tech sheets, and you'll be asking "but... Where's my tutorial? ".

Avarok wrote:Uh... Intel has long mode? I haven't seen a 64-bit intel CPU on the shelf yet.

I took it off the shelf last year June and put it in my computer, hope you don't mind...

paging in long mode seems to require about 3 extra tables but isn`t very clear about how to implement this

Actually, only two extra tables. There's no essential difference between 32-bit and 64-bit paging (64-bit entries instead of 32 bit ones, and as said, two extra tables)

The intel manuals will tell you fine how those tables fit together. You must only write the necessary code. If you can do 32-bit paging, you can do 64-bit paging with little extra effort.

I suggest you read the manuals since your reply suggests you didn't even try to comprehend it.