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How would one go about addressing more than 4gigs of memory?
I have seen many server boards that can address 32-gigs to a terabyte of memory? T

hey aren't in protected mode are they?
If so, what are they doing that allows the insane amount of memory addressing potential?

64-bit? long mode?

PAE (Physical Address Extension) or longmode.

...or PSE-36 (36-bit page size extensions)...

they are all right:
there are 2 ways of addressing more than 4GB of memory:
1) Page Size Extension +36 (PSE-36) this system is based on the older PSE, but isnt used much

2) Physical Address Extension (PAE) -- this extension was added around P6 (iirc both methods were added around the same time) -- if you use LMode, you must use a modified form of PAE (all paging is done through PAE)

these are both extensions to the paging system, and both work in PMode,

LMode is the 64bit operating mode, and always uses paging with (a modified form of) PAE (under LMode, neither paging nor PAE can be disabled)

PAE is the most common and flexible way to do it, and quite simple once you understand how it works (and can expand... which is why its used under LMode)

all intel CPUs since the P6 (that is the core used by both the Pentium Pro and the PentiumII) have had 36 address lines, allowing them to access at least 64GB of memory, chips capable of using LMode, can address more than that (the LMode system allows the chip to be very flexible as to how much it can actually address) but PAE extends very well to allow as many physical addresses as necessary, both in PMode and in LMode


for more information read:
3A:3.6.1 -- paging options
3A:3.8 -- using PAE
3A:3.9 -- using PSE-36
3A:3.10 -- using PAE in LMode


edit:
if you dont have the manuals, order them for free at the address link in my signature:

Thanks a ton guys.
That cleared alot of stuff up.

and I'll definitely grab those manuals.

Hey
Does any body know, how to access memory more than 4GB by making PAE bit enable.

I am trying hard but ultimately got the following error.

do you have paging enabled?
do you have the correct page tables?

Yes
i have enable PG bit of CR0 register also PAE bit of CR4 register. Also made page tables. PAE needs 4 levels of the page tables. Please correct if i go wrong.

Has your version of bochs been compiled with PAE support?

Ok - looking at the instruction just before the fault, you have:
eax is 0x80000011. If I understand correctly, are you trying to store data at the location pointed to by ds:[eax]? If so, 0x80000011 needs to be paged in. This is backed up by the fact that CR2 is loaded with that address.

Cheers,
Adam

prayag.ganoje wrote:Yes
i have enable PG bit of CR0 register also PAE bit of CR4 register. Also made page tables. PAE needs 4 levels of the page tables. Please correct if i go wrong.

As far as the intel manuals tell me, PAE requires 3 levels of tables - or if you like, four sets of a page directory (2nd level) + tables (1st level), and a structure (3rd level) that holds the location of each.

Only in long mode, you will need 4 levels.