Hi,
sancho1980 wrote:32 bits can address 2^32 bytes, 4 gigs if you will
but wait...
With 32-bits you can access 4 GB of physical address space. However "physical address space != RAM" - usually there's about 380 KB of legacy stuff below 1 MB and a hole for memory mapped PCI devices, APICs, the BIOS ROM itself, etc just below 4 GB. The size of this second area can be anything (depending on your chipset, BIOS and devices) - 512 MB and 1 GB are common.
For a computer with 4 GB of RAM, you might only be able to access half of RAM with 32-bit addressing. Depending on your chipset/BIOS the extra RAM may be accessable above 4 GB.
I should point out that most CPUs (Pentium II and later?) support PAE and PSE-36. Both of these are different ways of doing paging that allow the OS to use 36-bit physical addresses (up to 64 GB of physical address space).
sancho1980 wrote:and what happens with the video ram? where is it mapped? when i write to b8000, am i writing the memory of my video adapter or my system memory? what if my video adapter has 256 or more megs of ram? do i have to take that from the addressable ram too???
First, you could have a (purely theoretical) device with 512 MB of RAM in it, where the device's RAM can only be accessed via. I/O ports and can't be mapped into the physical address space at all. Alternatively, you might not be able to access the device's RAM at all (for e.g. a large cache in a hard disk controller).
For PCI, when the CPU tries to access something in the physical address space the memory controller checks to see if it's RAM or not. If it's not RAM it sends the access to the PCI bus, where PCI bridges route the access to a certain bus segment and devices on that bus segment may respond to it.
Usually, for a video card the PCI bridges route accesses to the area between 0x000A0000 to 0x000BFFFF to the bus segment that the video card is on. Usually the entire video display memory is also mapped into the "PCI device hole" below 4 GB, and accesses to this area are also routed by bridges to the bus segment that the video card is on.
How the video card interprets these accesses depends entirely on the device. For example, when you write to 0x000A0000 to video card might AND it with something, then split it into bits and send each bit to a different 64 KB bank of display memory, so that an 8-bit write effects 8 different areas of display memory. Of course this also depends on how the video card is configured (which usually depends on which video mode it's in - the "8-bits split into 8 different areas" example is common for 16 colour modes). For something like bank switched video modes, it's common for 64 KB of display memory to be mapped at 0x000A0000 and another 64 KB of display memory to be mapped at 0x000B0000, so that when you write to 0x000A0000 the video card does "my_address = your_address - 0x000A0000 + bank_start_address" to figure out which address in it's RAM to use.
If video display memory is (also) mapped into the "PCI device hole" below 4 GB, then usually the video display memory is mapped "as is" with no strange addressing translations (but again, this is entirely up to the video card).
It's also common for the video card's registers to (optionally) be mapped into the physical address space, so that it's device driver can use memory accesses instead of I/O ports.
Then there's the IOMMU, which is a new thing that's built into the memory controller. It's capable of translating and restricting different accesses, so that (for e.g.) when the CPU asks for one address it's translated to a completely different address on the PCI bus.
Basically, when software asks to read or write to any address, the CPU can mangle the address or do other things with it (via. the segmentation and paging mechanisms), then the memory controller can mangle the address or do other things with it, then the PCI bridges route it somewhere, then the PCI device can ignore it or accept it (and mangle it or do other things with it).
Cheers,
Brendan
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