base_class: 00000001, sub_class: 00000001
BAR00: 00000000, BAR01: 00000000, BAR02: 00000000
BAR03: 00000000, BAR04: 0000C000, BAR05: 00000000
According to the specification, BAR04 should be the base address for Bus Master registers. But all other BARs are all zeros. IS THIS CORRECT???
By default, ATA Command block and control block registers are mapped to ISA. That's why I can use 0x1F0-0x1F7 and 0x170-0x177 to do PIO read/write. This is the "compatibility mode". If I switch to "native mode", does that mean the BARs will not be all zeros?
Do I have to swith to "native mode" in order to enable DMA for ATA drives?
Reading Specs does not always help
![Sad :-(](./images/smilies/icon_sad.gif)
Thanks in advance!