UDMA for ATA and lack of documentation

[XCHG]

It's been 2 weeks now that I have been searching for some official documentations and/or datasheets for working with ATA drives in UDMA mode. I have already downloaded ATA-1, 2, 3, 4, 6 and 7 specifications from T13; Implementation guide for Ultra DMA released in 1998 and 1999 by T13 and a lot more official documents but surprisingly, none of those are complete and almost 99% of them don't even describe physical region descriptors and etc. I was wondering if anybody has some real documents pertaining to UDMA modes of transfer for ATA drives.

[bewing]

The ATA part of the specification seemed pretty complete to me, in the ATA6 documentation -- you just make sure your UDMA modes are matched between the drive and the PCI bus controller, and then use the DMA read and write, instead of the PIO commands.

Do you mean real documentation on setting up the PCI half of everything? The base address and all that crap? The documentation costs $1500 (US), as I understand it. Unless you can pirate a copy, in secret! As I understand, they are strict about shutting down easily found free copies of the PCI specification. I have not found any free copies of the spec laying around for me to grab. Unless you find one, you'll just need to go with hearsay, like everyone else, I think.

[mathematician]

Do you mean real documentation on setting up the PCI half of everything? The base address and all that crap? The documentation costs $1500 (US), as I understand it. Unless you can pirate a copy, in secret! As I understand, they are strict about shutting down easily found free copies of the PCI specification. I have not found any free copies of the spec laying around for me to grab. Unless you find one, you'll just need to go with hearsay, like everyone else, I think.

You could try "PCI System Architecture" from Mindshare. Although not the official PCI documentation it gives a fairly full account of it. Like all these things, much of it is given over to the mechanical/electrical specifications, but chapters 17-19 in particular are of relevance. With specific reference to IDE, you could also try downloading:

http://pdos.csail.mit.edu/6.828/2006/re ... Master.pdf

[octavio]

http://pdos.csail.mit.edu/6.828/2006/re ... Master.pdf

I have read this doc and done some testing
the image corresponds to page 3 i found a bit confusing that
pci reads means disk write commands, so i recommend to read this doc
and also some source code like in the Kolibri OS.
also the steps 3 4 are reversed in another similar docs i have.
i tested to set dma on first and then send the IDE command
and this works.

[exkor]

You want latest official docs you pay money. In either case docs rarely contain any programing examples. ATA/ATAPI6, IDE Busmastering(about 5 pages) & PCI specs(about 5 pages) have everything to make DMA working. In yours another thread I gave working DMA example(lastlink).

Since you are likely to go further and continue with SATA then reverse engineering is the only way for you. SATA(native,achi...) specs are only available to limited number of companies.

[bewing]

You could try "PCI System Architecture" from Mindshare. Although not the official PCI documentation it gives a fairly full account of it. Like all these things, much of it is given over to the mechanical/electrical specifications, but chapters 17-19 in particular are of relevance.

Thanks for the links. I think I am intending to "fake it" with my OS for as long as possible, before I start spending money on reference materials. There are sooooo many things to get working, before I need to polish up the last little details, and make sure I have all my "I"s dotted, as it were. Who knows -- maybe by the time I've got the thing almost done, I'll be willing to spend $1500 for the PCI 4.7 specification, or whatever.

[XCHG]

mathematician,

Thank you for the PDF file but I already had it and if you have looked at it yourself, you will see that it is not that much of a help!

Well I don't know what to say but the problem still exists! By the way, can anybody explain to me where those "base" addresses come from when talking about for example "Descriptor Table Pointer Register". The "Descriptor Table Pointer Register" in the primary channel has the address of Base + 0x04 but what is the base?

[mathematician]

The base address for the primary IDE channel is probably 0x1F0, and for the secondary channel 0x170 (page 2 of the pdf), but you would need to interrogate PCI configuation space to be sure of that fact. To find out how to do the latter you will need to look on the osdev or osfaq wiki, or fork out £10 and download the above mentioned book (PCI System Architecture).

[XCHG]

mathematician,

I highly doubt that the base address mentioned in the IDE bus mastering PDF file is the base address of the IDE controllers (primary and/or secondary). For example, the IDE Bus Master Command Register has the Address Offset of Base + 0x00 which should then be equal to the base. The base port address of the primary IDE controller is 0x000001F0 and for the primary it is 0x00000170 BUT the offset of 0x00 from these base addresses will be the DATA register for the IDE controller and not any of the IDE Bus Master registers let alone the Command Register whose offset from the base of the primary and the secondary IDE controllers is 0x07.

[JAAman]

Do you mean real documentation on setting up the PCI half of everything? The base address and all that crap? The documentation costs $1500 (US), as I understand it. Unless you can pirate a copy, in secret! As I understand, they are strict about shutting down easily found free copies of the PCI specification. I have not found any free copies of the spec laying around for me to grab. Unless you find one, you'll just need to go with hearsay, like everyone else, I think.

You could try "PCI System Architecture" from Mindshare. Although not the official PCI documentation it gives a fairly full account of it. Like all these things, much of it is given over to the mechanical/electrical specifications, but chapters 17-19 in particular are of relevance. With specific reference to IDE, you could also try downloading:

http://pdos.csail.mit.edu/6.828/2006/re ... Master.pdf

iirc, both intel and MS (both founding members of PCIsig) have the specification for download on their websites (though its easier to find on intels site) -- unless that has changed (been a few years since i saw it)

both companies are very good at providing documentation

[bewing]

I highly doubt that the base address mentioned in the IDE bus mastering PDF file is the base address of the IDE controllers (primary and/or secondary).

As I said, this is PCI information. It does not come from querying the disk. You have to query the PCI bus, find the Bus Mastering PCI disk controller, and get its configuration space data. The "base address register" (BAR) that you want is contained in the configuration space for the PCI disk controller. See the wiki article: http://www.osdev.org/wiki/PCI

It is a many step process, and not simple to do.

[exkor]

I noticed here, nobody told about PCI IDE Controller. Maybe you dont have this 5 pages document? http://suif.stanford.edu/~csapuntz/specs/pciide.ps

this code looks for PCI devices:

Code: Select all

FASM:

pci_addr_port  = 0cf8h
pci_data_port  = 0cfch 

;16bit mode
 ;ckeck PCI BIOS 2.0+ support
  mov  ax, 0b101h
  int  1ah
  jc   .error      ;no PCI BIOS
  cmp  ah, 0
  jne  .error      ;no PCI BIOS
  cmp  dx, 4350h
  jne  .error      ;no PCI BIOS
  test al, 1
  jz   .error      ;no supported method
  mov  [pci_busses+2], cl

pci_busses: dd 0                   

;32bit mode
scan_pci_devices:
  mov  edx, [pci_busses]
  lea  eax, [8000ff00h+edx+(1 shl 8)]   ;EAX = highest device
.find_device:
  sub  eax, (1 shl 8)                   ;change to next device
  mov  edx, pci_addr_port
  mov  edi, eax       ;save bus,dev,func,reg in EDI
  out  dx, eax
  add  edx, pci_data_port - pci_addr_port
  in   eax, dx
  cmp  eax, -1
  je   .check         ;possible device is not valid, go to next

    mov  edx, pci_addr_port
    lea  eax, [edi+4*2] ;register 2
    out  dx, eax
    add  edx, pci_data_port - pci_addr_port
    in   eax, dx
    ;eax = classcode

    shr  eax, 16      ;eax=classCode & subClass; no progIF or revision
    cmp  ax, 0101h    ;IDE
    je   .ata
    cmp  ax, 0105h    ;ATA with DMA
    jne  .check
  .ata:
    ;do the job of finding BARs here                                              

.check:
  mov  eax, edi
  cmp  edi, (1 shl 31); - (1 shl 8)     ;if we reached the end - lowest device
  ja   .find_device                     ;no
ret                                               

http://www.osdev.org/osfaq2/index.php/W ... n%20PCI%3F

added: you'll also need "pci local bus" specs,(300+ pages) start with chapter 6. rev3 was available thru google

[XCHG]

exkor,

Thank you for the PS file. I downloaded GSView but I don't have time to download the ~9 MB binary files for the engine so could you or somebody else, please, convert that to a document type and attach it to this post? I'd really appreciate it.

bewing,
Thank you for all the information. I had read about the BAR before but had not idea what it was.

[exkor]

i couldn't find pdf (but I got it on my computer).
Enter "pciide" in google and use "View as text" option
picture attached

edited: ok here is one http://www.bswd.com/pciide.pdf
same file is available at http://www.osdever.net/cottontail/#ATA and many others

[XCHG]

exkor,

Thank you so much. I appreciate your help.