Understanding VGA...

[JJeronimo]

I'm currently cross-reading some documents about the VGA hardware workings but there are some points where I can't catch it...

First: why does FreeVGA says that the graphics controller does the interface between the host system bus and the video memory, but the "Graphics Registers" include fields related to the rasterization of the display memory? (such as the 256-Color Shift Mode and the Shift Register interleave Mode fields) Yet, the Memory Plane Write Enable, Chain 4 and Odd/Even Host Memory Write Adressing Disable fields are on sequencer registers, why? Doesn't make sense!

Then, I don't understand how the hardware mixes the "addressing modes" with the "Read Modes" and the "Write Modes"... Are the read and write modes only valid when in normal addressing mode? Also I don't understand the difference between Chain 4 mode and Odd/Even... I've read the descriptions in freevga but it seems the same thing! :

Chain 4 -- Chain 4 Enable
"This bit controls the map selected during system read operations. When set to 0, this bit enables system addresses to sequentially access data within a bit map by using the Map Mask register. When setto 1, this bit causes the two low-order bits to select the map accessed as shown below.
Address Bits
A0 A1 Map Selected
0 0 0
0 1 1
1 0 2
1 1 3"
O/E Dis. -- Odd/Even Host Memory Write Adressing Disable
"When this bit is set to 0, even system addresses access maps 0 and 2, while odd system addresses access maps 1 and 3. When this bit is set to 1, system addresses sequentially access data within a bit map, and the maps are accessed according to the value in the Map Mask register (index 0x02)."

From http://www.osdever.net/FreeVGA/vga/seqreg.htm

Either it's really difficult or the thing is very very badly explained...


Now, what's the problem in programming the display memory when a pixel spans across all the planes? Why don't we just enable Chain 4 mode?

And... what are the things that people usually call "planar mode" and "linear mode"?

JJ

[Combuster]

Either it's really difficult or the thing is very very badly explained...

Wrong: for FreeVGA, its both

First: why does FreeVGA says that the graphics controller does the interface between the host system bus and the video memory, but the "Graphics Registers" include fields related to the rasterization of the display memory? (such as the 256-Color Shift Mode and the Shift Register interleave Mode fields) Yet, the Memory Plane Write Enable, Chain 4 and Odd/Even Host Memory Write Adressing Disable fields are on sequencer registers, why? Doesn't make sense!

First of all, the layout of the VGA 'sub-chips' isn't completely logical from the programmers perspective. For writing to memory, the data is apparently passed through both the GC and the Sequencer (as both have registers regarding such operations), for display, almost all chips have a take in the business. You can still make a pretty good distinction between registers dealing with the host-videomemory link and the videomemory-display link. A wild stab at how this happened to be is that the sequencer operates as the memory controller, so that all reads and writes to both connectors on the card are routed through here. Most likely the latest nvidia card doesnt do things this way anymore.
In essence, forget about chip purposes. Thats like pretending the existence of an utopia.

Then, I don't understand how the hardware mixes the "addressing modes" with the "Read Modes" and the "Write Modes"... Are the read and write modes only valid when in normal addressing mode? Also I don't understand the difference between Chain 4 mode and Odd/Even... I've read the descriptions in freevga but it seems the same thing! :

There are two steps involved.
1: the address provided by the host is translated to an address in video memory, and possibly a mask for each of the planes depending on the addressing mode.
2a: for writes, the latches are read, the written data is transformed according to the current write mode, and the output is sent to the memory. The planes that are actually written depend on the plane mask register and the mask generated in step 1 (which are afaik ANDed together).
2b: for reads, the requested address in video memory is read and the result is computed according to the read mode. The plane that is accessed depends on a register (planar mode) and/or the address (odd/even, chain 4). I haven't tested out thoroughly how everything works here, so you might want to be conservative and leave the read mode and read plane set to defaults when using oddeven or chain4 addressing.

Now, what's the problem in programming the display memory when a pixel spans across all the planes? Why don't we just enable Chain 4 mode?

Chain 4 just selects one plane out of the possible four when writing. The net effect is that a pixel spread over planes is described in 4 addresses rather than just one, and that you don't need to bother with changing the registers that select which one is being written/read.

And... what are the things that people usually call "planar mode" and "linear mode"?

planar mode: both odd/even and chain4 addressing are disabled. The address provided by the processor is mapped directly to video memory, and the read/write modes work as in the text book. This is basically the direct mapping how the VGA's video memory really works.

linear mode: Chain 4 addressing. One byte written or read from the VGA maps to exactly one byte on one plane in video memory. Normally this implies 256 color modes where one byte maps to exactly one pixel. Main advantage: easiest to program.

There is a (hopefully) more reader-friendly piece of vga documentation on the wiki: VGA Hardware (I wrote it, all comments welcome ) . If you want some practical advice on daily vga programming you might want to consider reading "Graphics Programming Black Book" as well (freely downloadable as pdf somewhere)

HTH.

[JJeronimo]

First of all, thanks for the information... I was getting really confused about this...

First of all, the layout of the VGA 'sub-chips' isn't completely logical from the programmers perspective. For writing to memory, the data is apparently passed through both the GC and the Sequencer (as both have registers regarding such operations), for display, almost all chips have a take in the business. You can still make a pretty good distinction between registers dealing with the host-videomemory link and the videomemory-display link. A wild stab at how this happened to be is that the sequencer operates as the memory controller, so that all reads and writes to both connectors on the card are routed through here. Most likely the latest nvidia card doesnt do things this way anymore.
In essence, forget about chip purposes. Thats like pretending the existence of an utopia.

Ok, ok... I had already read this in you article in the Wiki, but I hadn't understood to what extend this was true...

There are two steps involved.
1: the address provided by the host is translated to an address in video memory, and possibly a mask for each of the planes depending on the addressing mode.
2a: for writes, the latches are read, the written data is transformed according to the current write mode, and the output is sent to the memory. The planes that are actually written depend on the plane mask register and the mask generated in step 1 (which are afaik ANDed together).
2b: for reads, the requested address in video memory is read and the result is computed according to the read mode. The plane that is accessed depends on a register (planar mode) and/or the address (odd/even, chain 4). I haven't tested out thoroughly how everything works here, so you might want to be conservative and leave the read mode and read plane set to defaults when using oddeven or chain4 addressing.

Thanks... that's enough to make my own experiences...

Chain 4 just selects one plane out of the possible four when writing. The net effect is that a pixel spread over planes is described in 4 addresses rather than just one, and that you don't need to bother with changing the registers that select which one is being written/read.

Yes... But if the Chain4 offset is calculated as offset = addr >> 2; (as I read in the wiki article), we can use word or doubleword instructions to modify many bits at once...

And... what are the things that people usually call "planar mode" and "linear mode"?

planar mode: both odd/even and chain4 addressing are disabled. The address provided by the processor is mapped directly to video memory, and the read/write modes work as in the text book. This is basically the direct mapping how the VGA's video memory really works.

linear mode: Chain 4 addressing. One byte written or read from the VGA maps to exactly one byte on one plane in video memory.

And Odd/Even does more or less the same thing but writes to two planes at once (uses the low order bit to select between odd and even planes and then writes to both... that's what I hadn't understood), right?

Normally this implies 256 color modes where one byte maps to exactly one pixel. Main advantage: easiest to program.

Implies? Why? Are you talking about the cases where the Chain 4 bit influences video output?

There is a (hopefully) more reader-friendly piece of vga documentation on the wiki: VGA Hardware (I wrote it, all comments welcome ) .

It's still very vague about the distinction (or should I say uncertainty?) between the Chain4 / O/E busyness and the Write/Read Mode busyness...

If you want some practical advice on daily vga programming you might want to consider reading "Graphics Programming Black Book" as well (freely downloadable as pdf somewhere)

Thanks... I found it...
I'll first make some tests and then I'll take a look at the book...




Conclusion:
I surely don't want to use Chain4 mode because it's workings vary across different implementations. But in this case I don't understand: Why are there some standard modes that need to use Chain 4?

Odd/Even may seem interesting after some tests... (but hopefully many many people made the same tests already) Anyway, perhaps it's possible to speed-up some read and writes compared to planar modes (If the memory plane write enable field really do have some effect in Odd/Even "planar mode")...

JJ

[Combuster]

Chain 4 just selects one plane out of the possible four when writing. The net effect is that a pixel spread over planes is described in 4 addresses rather than just one, and that you don't need to bother with changing the registers that select which one is being written/read.

Yes... But if the Chain4 offset is calculated as offset = addr >> 2; (as I read in the wiki article), we can use word or doubleword instructions to modify many bits at once...

Only QEmu does it that way, and it is the wrong way. On real cards and the better emulated implementations the offsets into video memory go in steps of 4 - i.e. when writing a series of bytes first plane 0 at offset 0 is written, then plane 1 at offset 0, then plane 2, 3, then plane 0 at offset 4.

Normally this implies 256 color modes where one byte maps to exactly one pixel. Main advantage: easiest to program.

Implies? Why? Are you talking about the cases where the Chain 4 bit influences video output?

Only bochs is stupid enough to have chain4 influence video output. The real story is that for a true linear mode the sequencer+crtc are set up so that data that is written linearly is also displayed in a linear fashion, i.e. all the bits for one pixel, then all the bits for the next. Since the standard shift mode for 16-colors expects each pixel spread over 4 bytes, the bits that make up one pixel do not appear contiguous and the resulting mode isn't truly linear anymore. for 256 colors, all of the 8 bits are located in the same byte and all the pixels appear unscrambled in memory. Hence, linear mode implies a certain display setting, namely the 256-color shift mode bit being set. (You can set this for 16 colors as well, which will give you a 16-color linear mode, but its non-standard and output will depend on the card's byte order)

There is a (hopefully) more reader-friendly piece of vga documentation on the wiki: VGA Hardware (I wrote it, all comments welcome ) .

It's still very vague about the distinction (or should I say uncertainty?) between the Chain4 / O/E busyness and the Write/Read Mode busyness...

Thanks, I'll look at that

Conclusion:
I surely don't want to use Chain4 mode because it's workings vary across different implementations. But in this case I don't understand: Why are there some standard modes that need to use Chain 4?

Chain4 is the tricky bit: both bochs and qemu emulate it wrongly. VirtualPC is closer to the true behaviour, but consistent behaviour is unfortunately only found on real hardware. In standard bios modes, Chain4 is used in combination with a series of other settings, among which 256 colors and dword mode. Said wrong implementations make up with more bad stuff to make mode 13h work as expected. The result is that when you set all registers to mode 13h (320x200.256 linear), it works on all emulators. When you disable chain4 and the related bits, everything works in planar mode as expected. However you should not try to change only a few of those crucial bits as bochs and qemu will start showing completely wrong behaviour.
So far, I only found one difference among real cards: its related to using an non-standard shift mode in relation to the 256 color enable bit. However, in normal practice you shouldn't encounter that, and in case you wonder, FreeVGA has a pageful on this behaviour as it is in itself consistent.

Odd/Even may seem interesting after some tests... (but hopefully many many people made the same tests already) Anyway, perhaps it's possible to speed-up some read and writes compared to planar modes (If the memory plane write enable field really do have some effect in Odd/Even "planar mode")...

Odd/Even mode is one of the things I haven't tested thoroughly. The main disadvantage of oddeven/chain4 addressing compared to planar mode is that you can only access part of the video memory (50% in odd/even mode, 25% in chain4 mode)

If you want my testset, it is in the current alpha build used as the boot program. You will need to look at the code to see what registers (combinations) it is actually testing. (downloads + source on my website)