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Hi all,
Lately I've written procedures to detect devices connected to PCI. I'm reading 64 B of data, but I know that there is more to it (192B) with informations specific to device. Can anyone tell is it possible to find some documentations about this additional data ?
Another thing. How can I communicate with devices by PCI? For example I've detected HDD controller connected to PCI. How to talk with HDD by controler through PCI? Is it possible or should I use "in" and "out" instructions for all devices in computer ?

How you talk to a device depends on the device. That's what you need device drivers for, and unfortunately you need to write one for each device you want to support (some devices are compatible with other devices, but that's it).

As for talking to devices, it depends on the device. The PCI configuration data will give you memory and I/O ranges that you can use to talk to the device, but what you do with those depends on the specific device in question.

The basic idea is that you take the vendor or device IDs (and possibly class ID as well) and match them against your available drivers, which will then figure out what to do with the device.

crackers wrote:Lately I've written procedures to detect devices connected to PCI. I'm reading 64 B of data, but I know that there is more to it (192B) with informations specific to device. Can anyone tell is it possible to find some documentations about this additional data ?

You should refer to the datasheet to find out, as it is device-dependent.

Another thing. How can I communicate with devices by PCI? For example I've detected HDD controller connected to PCI. How to talk with HDD by controler through PCI? Is it possible or should I use "in" and "out" instructions for all devices in computer ?

Either with port i/o or memory accesses. Which ports/addresses are used can be found in the pci configuration space.

mystran wrote: As for talking to devices, it depends on the device. The PCI configuration data will give you memory and I/O ranges that you can use to talk to the device, but what you do with those depends on the specific device in question.

So by communicating with PCI I can only get and set informations, not "talk" with device right ?

crackers wrote: So by communicating with PCI I can only get and set informations, not "talk" with device right ?

Well, PCI is a bus. What you are talking about is the PCI configuration space. PCI configuration space allows you to figure out what kind of devices there are, and when you start drivers for them, they can look into the configuration space for the necessary I/O and memory addresses to talk to the device.

In theory, BIOS is supposed to configure PCI devices for you, so in many cases you only need to read the configuration space. I'm no expert though, so I guess somebody else here can explain that stuff in more detail. I know just enough to get some devices detected and drivers running, which includes reading vendor/device IDs, memory and I/O addresses, and BIOS configured IRQ assignment.

Hi
As mystran said PCI is just a bus to connect the devices. Through PCI you can get necessary information about the bus where it is connected, what type of device is connected. but to communicate to the devices you need to write drivers for those devices. The drivers are responsible for communicating to those devices. For example to access the hard disk you need to study the specific datasheets. However it's made easy for hard disk, they follow certain standards so you don't have to write drivers for each type of hard disk. Suppose you want to write drivers for sound card, it's difficult you have to study the datasheets given along with sound cards. I hope this will help[ you.
cheers
pradeep

After reading the responses to this (a question I have need answering to aswell), I believe the fog has lifted a bit in the land of PCI.

If i understand this correctly now, all that should be done to the PCI config space is to enumerate the devices and their respected functions and read the memory i/o locations for the device being activated, then that memory address area is where the driver will do its thing in.

The only device type I know that has more configuration space than those 64 bytes is a PCI bridge, which is scarcely documented but required for enumeration. You can for the coming few years assume that either the BIOS set it right or the OS living next to yours did it right.

For detect device use PCI Configuration Space
PCI Configuration Space have 256 B
Head type 00 have 64 B but above you can find Capabilities List or specificity registers.

Exspress PCI can have greater then 256 B.


When you find device you can read BARs (Base Address Registers)
In the register address I/O or Memory (Memory Mapped I/O).

However "talking"? Specific of kind device. But do it over I/O or Memory write to BAR.

For HDD controller connected to PCI. Read "PCI IDE Controller
Specification", "Programming Interface for Bus Master IDE Controller", "ATA/ATAPI".
it is easy.

Hi,

Just a few quick notes....

@Cracker: PCI configuration space is mostly only useful for device identification, resource assignment and power management. There are a few exceptions (bridges, especially the PCI to LPC bridge), but you shouldn't need to worry about them.

@Candy: PCI Express introduced a new PCI configuration space access mechanism, where the configuration space for each device is memory mapped by the PCI host controller (accessed via. normal reads/writes to the physical address space rather than I/O ports), and each device's configuration space can be up to 4 KB. Note: I got this information from a recent Intel chipset datasheet (including enough information to access PCI configuration space via. this mechanism) - I haven't been able to obtain the relevant information from PCISIG (as they're theives).


Cheers,

Brendan

Brendan wrote:@Candy: PCI Express introduced a new PCI configuration space access mechanism, where the configuration space for each device is memory mapped by the PCI host controller (accessed via. normal reads/writes to the physical address space rather than I/O ports), and each device's configuration space can be up to 4 KB. Note: I got this information from a recent Intel chipset datasheet (including enough information to access PCI configuration space via. this mechanism) - I haven't been able to obtain the relevant information from PCISIG (as they're theives).

I'm still waiting on my PCI and PCI-Express system architecture books, which I ordered because the reviews said "It's practically a copy of the PCI-SIG document!". They're a lot cheaper

They were ordered start of last month, should've been here 27th of July, still haven't arrived...

Do you have a link / reference to the chipset datasheet?

ya, i would get the intel documentation, as intel is a/the founding member of PCISIG, and gives away all documentation free (intel and MS both do, but intels is easier to find) unfortunately i havent been there since the site redesign, and so all my links are bad...

but if you go to developer.intel.com, select the 'products and technology' tab and select 'chipsets' (center column) and select the appropriate category for what your looking for, then select the chipset, and on the technical documentation tab, there will be a list of datasheets (amongst other documents) -- documentation for all intel products can be found in a similar method -- i just looked myself and was quite surprised at how easy it was to use (much easier than the old website)

Hi,

Candy wrote:I'm still waiting on my PCI and PCI-Express system architecture books, which I ordered because the reviews said "It's practically a copy of the PCI-SIG document!". They're a lot cheaper

PCISIG's pricing seems to be intended for large hardware manufacturers - open source programmers who don't care about mechanical/electrical details don't fit very well in their pricing....

Candy wrote:Do you have a link / reference to the chipset datasheet?

It's section 3.3.2 "PCI Express* Enhanced Configuration Mechanism" in the datasheet for Intel's 82975X Memory Controller Hub (975X Chipset) - document number 310158-001.

I'd guess similar details could also be found in other datasheets for Intel chipsets that support PCI Express.

The new configuration space access mechanism is actually nice (it's not a badly designed pain in the neck). There's a "PCIEXBAR" register that determines the base address of the configuration space mapping (in the host controller's configuration space at offset 0x48). After that's setup each device's 4 KB of configuration space is accessed at an address that can be calculated with "base_address + (bus << 20) + (device << 15) + (function << 12) + offset".


Cheers,

Brendan