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Hi All,

I am just making some optimisation changes to my paging mechanisms and was wondering about how best to optimise things.

As suggested in the IA32 manuals, I have got my kernel sitting in a single, 4MB global page. I am unsure, however, how much to make use of the 'global' flag. If I make too much use of this flag (such as if I automatically use it for any kernel heap pages allocated), presumably I will increase the chance of TLB misses when switching to user-space tasks.

Is it reasonable to assume that the use of this for the kernel code and kernel stack pages is optimal?

To give you some background information, I intend to do the standard 'each process in its own memory space, flat segmentation, kernel mapped in to every user-space' type thing. Generally, I am using 4kb pages for everything other than the kernel image itself.

Any thoughts appreciated,
Adam

well, when you switch address spaces, the non-kernel TLBs will be flushed and you'll suffer tlb misses the moment you return to userspace. Regarding that its better to preserve as much tlbs as you can.
The point of 4M pages is that they take 1 tlb entry instead of 1024 entries, which minimizes filling of the TLBs with kernel pages (and hence reduces further tlb misses due to elimination of pages which need to be reloaded later), the downside is that it reserves a lot of memory which may be wasted.

So, there are two means of optimizing:
1: maximizing the use of the Global flag
2: balancing out 4M and 4K pages to optimally use the TLB and memory (which is basically a trade-off)

Thanks for this. My concern was that 'over-using' the global flag could be detrimental to performance.

I only ever intend to use the one 4MB page, so understand from another look at the Intel docs that the kernel page should *never* be flushed by reloading CR3, as there is a separate TLB for 4MB pages.

Looks like I should go for it and use that global flag as much as possible in kernel / driver space.

Cheers,
Adam