Hi,
digo_rp wrote:guys just to understand how i8259 works in AEOI MODE
I´m using right eoi mode I don´t understand I set the both i8259 for AEOI
I don´t need to send the eoi command at the end of each interrupt, right ?
First, the slave PIC can't ever be used in AEOI mode. I can't remember the actual reason for this - something to do with messing up it's communications with the master PIC.
Also, AEOI mode won't work with level triggered interrupts (e.g. from PCI devices). In this case I would expect an interrupt flood because the device's interrupt line is still asserted when the PIC chip does the EOI.
This means that for most computers you can set the master PIC as AEOI, but for some computers you can't (depending on which PIC inputs are used for PCI IRQs). Also, for most modern motherboards one of the PIC inputs is used for an ACPI SMI interrupt that is usually level triggered. This SMI interrupt is disabled until the OS enables "ACPI mode" (which may or may not happen).
Conceptually, outside the PIC chips there's another chip that converts level triggered interrupts into edge triggered interrupts suitable for the PIC chip's inputs. This is called the "ELCR" (Edge/Level Control Register) and can be found at I/O ports 0x04D0 (for the master PIC) and 0x04D1 (for the slave PIC). It should be possible to read from I/O port 0x04D0 and check if any bits are set to determine if any IRQs are level triggered.
Of course at boot these ELCR registers will be configured by the BIOS according to what it knows. It's entirely possible for the BIOS to do this wrong. For example, if you've got an ISA sound card using IRQ 9 (edge triggered) and the BIOS is trying to use IRQ 9 for a (level triggered) PCI IRQ then an operating system like Windows will change the PCI IRQ to something else (e.g. IRQ 5) to avoid conflicts (and adjust the relevant ELCRs to suit).
Also, this depends on how old the computer is. For "ISA only" systems you shouldn't have any ELCRs or any level triggered interrupts. For any system with EISA the ELCRs will be present as EISA uses level triggered interrupts and this was part of the EISA standard. For systems with PCI the ELCRs should be present (but it's possible that the chipset uses it's own non-standard method instead, especially for older PCI chipsets).
My advice - AEOI mode is more trouble than it's worth, and it's probably a good idea to wait until your OS works before worrying much about optimizations like this.
Cheers,
Brendan