OSDev.org

Posted: **Mon Oct 02, 2006 11:03 pm**

I'm in need of some help setting up and loading a TSS.

I have the entry set up in the GDT, but whenever I issue the LTR assembler command, Bochs gives the warning 'fetch_raw_descriptor: GDT: index (ff57)1fea > limit (30)' and then I get a GP fault.

I have the TSS segment at GDT[5], so my LTR command is basically 'LTR 0x28'. I'm pretty sure that's right.

LTR takes the offset into the GDT as the argument, right?

I've inspected the GDT in the bochs debugger, and that shows the TSS as set up correctly, so I'm not too sure what I'm doing wrong. I've also tried 'LTR 0x05', but that gives a 'ltr: selector.ti != 0' error, and based on what I said above and looking at other OS code (NewOS, AMOS, TabOS), I'm pretty certain I'm doing it right.

If someone would be so kind as to review my code... I've been staring at this for a couple days and reading the Intel docs, but I'm at a loss as to what I'm screwing up here.

Just two links... the first one is to my GDT code, the next one is for my main kernel initialization routines (which is where the LTR statement is).

gdt.c

eduos.c

I'd appreciate any help on this one. Thanks.

Posted: **Tue Oct 03, 2006 12:03 am**

Hi,

I could be wrong (it's been a while since I've used LTR), but I think the LTR instruction accepts either a register or a memory address, and does not accept an immediate operand.

I assume that your code is loading whatever happens to be at "[0x28]" into the task register, instead of the value 0x28...

In NASM syntax this means that you could use:

Code: Select all

   mov ax,0x28
   ltr ax

Or, you could do:

Code: Select all

   section .data
LTRentry:   dw 0x28
   section .text

   ltr [LTRentry]

In (very rusty) AT&T syntax this is:

Code: Select all

   mov $0x28,%ax
   ltr %ax

Or:

Code: Select all

   section .data
LTRentry:   dw 0x28
   section .text

   ltr LTRentry

What you are trying to do is use an immediate operand (e.g. "ltr $0x28") but the assembler should refuse to assemble that because the CPU itself doesn't support it.

Cheers,

Brendan

Posted: **Tue Oct 03, 2006 2:59 pm**

Awesome, thanks! I got it working now. I knew something was wrong when I had to do 'ltr (%0)' to get it to compile, but I wasn't sure what exactly it was.

Time to brush up on my x86 assembly skills.

OSDev.org

TSS Troubles

TSS Troubles

Re:TSS Troubles

Re:TSS Troubles