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Hey all.
Im just curious...
At the moment, My IRQ Handler... sends EOI messages to PIC1 and PIC2 when an Interrupt is fired higher than 39. Obviously, this isnt right? right?.

If I want to be able to use the Interrupts provided to me by the Second PIC, would I not have to implement some check?

Like... Ok, the Cascading interrupt on PIC1 is firing! Time to check PIC2 for Activity?

Im just not really that sure?

This is all handled automagiacally by hardware, most probably in the north bridge.

As far as the PIC goes, first you set it up (mapping the IRQs is probably the only setup relevant for a modern PC, all other options are usually the same no matter what OS is running). Now add handlers, which must issue the correct EOI messages. The last thing to consider is masking and unmasking interrupts at the PIC (I do not mean cli/sti).

Thats it for the PIC. If you want more, use the LAPIC(s) and IOAPIC(s). The main concern for the actual handlers is telling the device (not the PIC) that you have dealt with the interrupt as this is done in a different way for every device.

Adding to those above, you might want to tell PIC whether you want edge or level triggered interrupts. As it is, there are systems where getting each PCI device it's own interrupt vector is impossible, yet APIC, if any, is buggy enough that you can't really use it.

Onto the next thing...
Anyone know any good websites explaining the FAT12 Filesystem?

zeii wrote:Anyone know any good websites explaining the FAT12 Filesystem?

google?
The official specs by Microsoft

Our very own OS FAQ, linked on its front page with the keyword "FAT12" ?