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Hi all,

i am trying to implement Paging which uses Trap or Interupt Gates, in stead of a simple Task switch.




When i exec. a command like "Int 0eh" (or when a Page fault is generated), the system fails so badly that it generates a double fault and this is only the case when he is running at CPL 3, if a page fault occourse at CPL 0, it simply works.

So probely he has a problem whit changing the Stack reg's to CPL 0, from CPL 3.

The weird part is that i am able to use a Call Gate (to go from Priv.Lv.3 to Lv.0), which should do the same thing and thus should also use SS0.



These are the used Entries:
IDT-0Eh:
dw offset hander 0-15
dw SYS_CODE_SEL ; Sel for GDT. RPL == 0
db 0
db 0xEE ; DPL 3, Interupt Gate, Present.
dw offset handler 16-31


GDT:
SYS_CODE_SEL: Liniear sel. so can access the enire 4 gigs.
dw 0xFFFF ; Limit 0-15
dw 0
db 0
db 0x9A ; Non-conforming. DPL 0, R/W
db 0xCF ; limit 16-19, BIG-flag, Granularity-bit.
db 0


The SS0. selector: Liniear sel. so can access the enire 4 gigs.
dw 0xFFFF ; Limit 0-15
dw 0
db 0
db 0x92 ; Ring 0, R/W.
db 0xCF ; limit 16-19, BIG-flag, Granularity-bit.
db 0


The Call gate, which does work...:
dw offset handler 0-15
dw SYS_CODE_SEL
db 0
db 0xEC ; DPL 3, Present, Call-gate.
dw offset handler 16-31


Another thing when i set the SYS_CODE_SEL to a Conforming code-sel, then he doesnt generate a Double Fault, but then he simply stays at CPL3, but then he still uses the same Stack.

Also all other interupts are still using Task-switch method.

What am i missing here?


Regards.
PyroMathic

Hi,

What you're saying is that if the CPU changes to a different stack as part of the interrupt, then your code fails.

I'd guess that you've got something wrong in the TSS's SS0:ESP0 fields which prevents the CPU from changing to the CPL=0 stack (or makes this stack overwrite something, or causes a page fault or something).


Cheers,

Brendan

Lo,

Yes that is probely the thing, the problem is that a "Call Gate" does work and if i have read the Intel Docs properly, then the operation should be identical.

Regards.
PyroMathic

Yes that is probely the thing, the problem is that a "Call Gate" does work and if i have read the Intel Docs properly, then the operation should be identical.

if the cpu can switch stacks btw 3->0 on a call gate then there is no reason it will fail on an interrupt gate, as the same mechanism is used in both cases.
i think there is something wrong in your interrupt setup code that makes cpu unable to handle the first excpetion that is generated when calling the int handler.

Another thing when i set the SYS_CODE_SEL to a Conforming code-sel, then he doesnt generate a Double Fault, but then he simply stays at CPL3, but then he still uses the same Stack.

this is the purpose of the conforming code segments. they are designed in order to be called from a less preveligied code.

Hi,

Problem was solved, apperently when the code enters Ring0 from ring3 the first time he generates a page fault. Cause of the Stack wasnt present... Now i got it fully working.

Ty for the help.

Regards.
PyroMathic