OSDev.org

Posted: **Sun Jan 08, 2006 6:29 am**

I don?t know when I?ve broken my apic code, but now it doesn?t work anymore

This is the code I use to activate the apic timer:

mov eax,[cpu_apic_count_val]
   and dword[APIC_BASE_ADDR++apic_regs_t.lvt_timer_reg],0ffffff00h or (not APIC_MASK_INT)
   APIC_TIMER_SET_COUNT eax
   or dword[APIC_BASE_ADDR++apic_regs_t.lvt_timer_reg],INT_SCHEDULER or APIC_TIMER_PERIODIC

These are some needed values:

Code: Select all

;----------------------------
macro APIC_TIMER_SET_COUNT val
{
   mov [APIC_BASE_ADDR+apic_regs_t.init_count_reg],val
}
;----------------------------

APIC_MASK_INT= 10000000000000000b
APIC_TIMER_PERIODIC= 100000000000000000b
INT_SCHEDULER= 0f0h

struc apic_regs_t
{
   .reserved1         rd 4
   .reserved2         rd 4
   .id               rd 4
   .ver            rd 4
   .reserved3         rd 4
   .reserved4         rd 4
   .reserved5         rd 4
   .reserved6         rd 4
   .tpr            rd 4
   .apr            rd 4
   .ppr            rd 4
   .eoi            rd 4
   .reserved7         rd 4
   .log_dest_reg      rd 4
   .dest_format_reg   rd 4
   .svr            rd 4
   .isr            rd 32
   .tmr            rd 32
   .irr            rd 32
   .esr            rd 4
   .reserved8         rd 28
   .icr_0_31         rd 4
   .icr_32_63         rd 4
   .lvt_timer_reg      rd 4
   .lvt_therm_sensor   rd 4
   .lvt_perf_mon_count   rd 4
   .lvt_lint_0         rd 4
   .lvt_lint_1         rd 4
   .lvt_error_reg      rd 4
   .init_count_reg      rd 4
   .current_count_reg   rd 4
   .reserved9         rd 16
   .div_cfg_reg      rd 4
   .reserved10         rd 4
   .size_t            rb 0
}

My scheduler doesn?t get called, but if I do "int INT_SCHEDULER" it works!

Posted: **Sun Jan 08, 2006 6:31 am**

I know that it is no problem with Bochs or Qemu, because I use the apic timer count for getting the bus speed and this works!

Posted: **Sun Jan 08, 2006 2:10 pm**

Without checking your code, the obvious question is: did you accidently forget to enable interrupts or accidentally disable them somehow?

Otherwise, the AND and OR opcodes in your first code block makes me a little curious. Can you do that on a memory mapped APIC register? What about just MOV'ing the right value into them as a one-shot setting like your APIC_TIMER_SET_COUNT macro does? 'cos working with them in memory (AND and OR) will mean your APIC is mis/half configured for the few moments until the AND and OR's complete. And I think you should verify whether or not the APIC is okay with that kind of thing and being configured in steps...

Posted: **Sun Jan 08, 2006 3:59 pm**

I found out that this piece of code is alright, because in an older version of my code I used the same code and it worked. So it has to be another piece of code which doesn?t work. I think that maybe I remap the page entry for the apic.

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