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I went through AMD's Tech Doc's and Intel's Tech Doc's
...and it seems that the x86-64 does not support pusha, so I was wondering if I should do a stack-based task switching mechanism without the pusha opcode or should I use TSS Task Switches, even through segmentation is completely removed in the x86-64?
And how would you recommend that I implement them?

Hi,

Long mode doesn't support hardware task switching, so you have to use stack-based task switches.

BobFrank wrote:And how would you recommend that I implement them?

AFAIK It's the same as it would be in protected mode. During initialization:

• * Build a single TSS (containing IST, ESP and ESP0)
  * Make a TSS gate
  * Do LTR

Then for each task switch:

• * Store everything on the stack
  * Switch to another stack
  * Set ESP0 in the TSS
  * Restore everything from the new stack

When a task is spawned you'd need to create a new stack for it that contains the values that will be restored by the task switch code (so it doesn't cause problems the first time the task is switched to).


Cheers,

Brendan

BobFrank wrote: I went through AMD's Tech Doc's and Intel's Tech Doc's
...and it seems that the x86-64 does not support pusha

That sounded completely surrealist at first sight, but yet

Using the PUSHA or PUSHAD instruction in 64-bit mode generates an invalid-opcode exception.

So i guess we'll have to explicitly push every register we want to be task-local.

That seems to be a step in the wrong direction to me

It indeed does not "exist" (it'll produce an invalid opcode if you do use it according to the AMD docs). I'm thinking they may have done this to make the programmer more aware of what you are actually doing. Consider the following:

PUSHA in 16 bit mode uses 16 bytes
PUSHA in 32 bit mode uses 32 bytes

PUSHA in 64 bit mode would use 128 bytes of memory (assuming it would also push R8-15, without it would be 64 bytes)

Of course you can build your own macro (PUSH64 & POP64?) that does it in 16 instructions (or less if you don't use certain registers). It may be an instruction waste, but then again enough address / memory space to play with...

Hopefully they'll let us know why it wasn't included.