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Nelson wrote: Map all the user memory as RW, U, P

Map some global memory for my libraries etc (Does the "Global" flag do this or should I just make it U, RW, P)

Map the kernel memory as R,S,P

Now a few questions arrise before implementation: Bits 12-31 in the PDEs and PTEs show
the address field now is this virtual of physical?

I don't get where the phys2virt
conversion goes on or how to map physical addresses to virtual ones.

Also which "permissions" take priority over what? eg(If a PDE is set as RW, U can a PTE in
the PDE be set as R, S?)

When in ring0 does the paging mechanism even do permission checks? Or can the kernel
access anything regardless of what flags are set?

Now can someone please explain to me when a VMM might become useful?
The only thing I can consider it for is finding a physical adddress for a page and
adding it to the PDE then Invalidating the PTE with whatever flags. Maybe as a sub
function of a "MapPage(phys,virt,flags)" kind of thing.

Candy wrote:

I don't get where the phys2virt
conversion goes on or how to map physical addresses to virtual ones.

Say, you have virtual address 0x12345678 in non-PAE mode. Then, 0x123 >> 2 = 0x048 is the index into the PDT (CR3, physical address). It looks up which page is referenced there (physical address) and looks in it for item 0x345 & 0x3FF = 0x345. That item references a physical page. In that physical page it references the address 0x678, which is the byte you wanted.

When in ring0 does the paging mechanism even do permission checks? Or can the kernel
access anything regardless of what flags are set?

The kernel can not access readonly paged memory. With a given bit it can do this for userlevel memory. There are more, iirc, but too many to list. See the one document you've been reading already .

Candy wrote: Say, you have virtual address 0x12345678 in non-PAE mode.
Then, 0x123 >> 2 = 0x048 is the index into the PDT (CR3, physical address).
It looks up which page is referenced there (physical address) and looks in it for item 0x345 & 0x3FF = 0x345.
That item references a physical page.
In that physical page it references the address 0x678, which is the byte you wanted.

You have to self-map the page tables and directories, that is, make them point to themselves.
The easiest way is at the top of memory. Place the PDT at 0xFFFFF000.
It doubles as PT for itself, and as well as page for itself.
Just by creating that one entry can you use it to add to the page tables.

Candy wrote: Keeping track of free pages, mapping and unmapping pages, keeping track of pages shared between processes
(COW, copy on write), allowing pages to be swapped out...

Good luck on getting that in one function (and if you succeed, it won't be good ).

AR wrote: IIRC, you've got that backwards, Ring 0 code ignores the user/supervisor
and readonly/writable unless you enable the 'Kernel level paging protection'
feature which you need to find with CPUID and enable by setting a bit in one of the control registers,
present is checked but I don't know about NX.

IIRC, you've got that backwards, Ring 0 code ignores the user/supervisor and readonly/writable unless you enable the 'Kernel level paging protection' feature which you need to find with CPUID and enable by setting a bit in one of the control registers, present is checked but I don't know about NX.

Would this be practical to enable if detected as a supported feature? I think I can see this protecting the kernel from the user and the user from the kernel as well which might not be such a bad thing

JAAman wrote: NX/XD/PE/Feature_With_A_Lot_Of_Names, is checked when the CPU loads a page into the instruction TLB: if NX is enabled, and set, it will refuse to load the page into the TLB (all other checks (except P) are made after it enters the TLB -- P & NX/XD/PE are the only permisions that cause the page to fail to load into the TLB), causing a #PF (AMD#2, pg173 (rev. 3.07))

if (type == code && NX) || (!p) then
  cause_pf();
else
  ....
end if;

Candy wrote: On the R/W + U/S + rw_in_s bit, if all is usually writable for the kernel and given that bit the userlevel bit is marked readonly, what's the entire point of marking something R/S ? It'd be a readonly thing that nothing would ever enforce. My guess is thus that that is an error, so that R/S for kernel-level would always be enforced.

Write Protect (bit 16 of CR0). Inhibits supervisor-level procedures from writing into user-level read-only pages when set; allows supervisor-level procedures to write into user-level read-only pages when clear. This flag facilitates implementation of the copy-on-write method of creating a new process (forking) used by operating systems such as UNIX*.

The page-level protection mechanism recognizes two page types:

• Read-only access (R/W flag is 0).
• Read/write access (R/W flag is 1).

When the processor is in supervisor mode and the WP flag in register CR0 is clear (its state following reset initialization), all pages are both readable and writable (write-protection is
ignored). When the processor is in user mode, it can write only to user-mode pages that are read/write accessible. User-mode pages which are read/write or read-only are readable; supervisor-mode pages are neither readable nor writable from user mode. A page-fault exception is generated on any attempt to violate the protection rules.

Nelson wrote: Okay I get how the virtual addresses are split up to find indexes in the PDE and PTEs, now when mapping do I put the full (physical)address wanted to be mapped in both the PDE and the PTE?

(Page-table entries for 4-KByte pages.) Specifies the physical address of the
first byte of a 4-KByte page. The bits in this field are interpreted as the 20 mostsignificant
bits of the physical address, which forces pages to be aligned on
4-KByte boundaries.
(Page-directory entries for 4-KByte page tables.) Specifies the physical
address of the first byte of a page table. The bits in this field are interpreted as
the 20 most-significant bits of the physical address, which forces page tables to
be aligned on 4-KByte boundaries.

int MapMemory(unsigned long phys, unsigned long virt, unsigned long flags);

Nelson wrote: Linear Address translation splits up the address and finds the index to PDEs and PTEs. Okay.
PHYSICAL addresses of the Page table go into the PDE and PHYSICAL addresses of the Page itself go into the PTE

What I am confused about is say you have

Code: Select all

int MapMemory(unsigned long phys, unsigned long virt, unsigned long flags);

How would I get the Physical address to "point" to the virtual addresses upon translation?

Thanks,
Nelson

int MapMemory(unsigned long phys, unsigned long virt, unsigned long flags) {
  unsigned int *pd = (unsigned int *)0xFFFFF000;
  unsigned int *pt = (unsigned int *)0xFF300000;
  int pd_offs = virt >> 22;
  int pt_offs = virt >> 12;

  // if there's no page table present
  if (pd[pd_offs] & 1 == 0) {
    // map one
    MapMemory(GetFreePage(), 0xFF300000 + (pd_offs << 12), some_flags);
  }
  // if there is a page present
  if (pt[pt_offs] & 1 == 1) {
    // unmap it and remap this one, or something else.
    AddFreePage(UnMapMemory(virt));
  }

  pt[pt_offs] = (phys & 0xFFFFF000) | flags;
  return 0;
}