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hello everybody, ... again

i am learning kernel development from bran's tuts and i created makefile to compile all the stuff and produce a flat binary image of the kernel.

here is the code of that makefile:-
everything goes fine till it compiles the file isr.c. it even compiles the next files (irq.c and so on...) and gives a object file. the script output for these files is, quite strange for me , as follows :-

make: Circular irq.c <- irq.c dependency dropped.
Circular keyboard.c <- keyboard.c dependency dropped.
ld -T link.ld entry_kernel.o main.o print.o gdt.o idt.o isr.o irq.o


although i get the results but cant interpret what does these lines mean. is there anything to worry about in the code.
please let me know if you want code of other files.

thanks in advance for any help.

cheers

[edit by candy] please use code tags in your replies since they make the output more readible [/edit]

Did you use tabs at the start of each gcc line?

You've specified the C file instead of the O(bject) file for the irq and keyboard rules.
So, irq.c depends on irq.c .. which creates the circular dependency. (irq.c depends on irq.c which depends on irq.c which depends on irq.c etc...)

Just make it:

Does that work?

moreover, you might like to know you can do template rules, where $< is the 'first prerequisite' argument and $@ the 'target' argument.


Is all you actually have to write: when building 'kernel', make will detect it needs main.o
# Since it has a rule to make <something>.o out of <something>.c, it will look for 'main.c', which do exists.
# It will thus substitute '$<' with 'main.c', $(flags) with their content and invoke 'gcc -Wall -O -fstrength-reduce -fomit-frame-pointer -finline-functions -nostdinc -fno-builtin -c main.c' for you
# same process is repeated with print.o, gdt.o, idt.o ...

If you need some 'custom' processing for some targets, you still can override the generic rule by something more specific.

Pype.Clicker wrote: moreover, you might like to know you can do template rules, where $< is the 'first prerequisite' argument and $@ the 'target' argument.

Code: Select all

HEADERS=foo.h bar.h baz.h
flags=-Wall -O -fstrength-reduce -fomit-frame-pointer -finline-functions -nostdinc -fno-builtin

%.o: %.c $(HEADERS)
        gcc $(flags) -c $<

kernel  : entry_kernel.o main.o print.o gdt.o idt.o isr.o irq.o keyboard.o 
    ld -T link.ld $?

Is all you actually have to write: when building 'kernel', make will detect it needs main.o
# Since it has a rule to make <something>.o out of <something>.c, it will look for 'main.c', which do exists.
# It will thus substitute '$<' with 'main.c', $(flags) with their content and invoke 'gcc -Wall -O -fstrength-reduce -fomit-frame-pointer -finline-functions -nostdinc -fno-builtin -c main.c' for you
# same process is repeated with print.o, gdt.o, idt.o ...

If you need some 'custom' processing for some targets, you still can override the generic rule by something more specific.

What does $? do? I know $^ refers to the objects given above, which is what you want (I think).

Make documentation chapter 10.5.3,Automatic Variables.

Solar wrote: Make documentation chapter 10.5.3,Automatic Variables.

$?
The names of all the prerequisites that are newer than the target, with spaces between them. For prerequisites which are archive members, only the member named is used (see section 11. Using make to Update Archive Files).

$^
The names of all the prerequisites, with spaces between them. For prerequisites which are archive members, only the member named is used (see section 11. Using make to Update Archive Files). A target has only one prerequisite on each other file it depends on, no matter how many times each file is listed as a prerequisite. So if you list a prerequisite more than once for a target, the value of $^ contains just one copy of the name.

So, I think $? is an error and $^ should be used.

Candy wrote: So, I think $? is an error and $^ should be used.

X_x n33d c0ff33 ...

thanks a lot everybody ...
i learnt the mistake that i have committed in the make script and i'd learnt something new about the make scripting and will definitely give it a try