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I know that changing CR3's value invalidates all TLB entries.
What about disabling and re-enabling paging ? Does this also invalidates all TLB entries ? (I guess it does)
Which one takes the less time ?

probably the same amount of time. What costs is the fact the TLB is empty (requiring additionnal cycles to re-fill it on demand), not the emptying process itself (basically, it asserts a signal line for one cycle and all the "valid" bits of all the entries are cleared simultaneously ...)

pini wrote: I know that changing CR3's value invalidates all TLB entries.
What about disabling and re-enabling paging ? Does this also invalidates all TLB entries ? (I guess it does)
Which one takes the less time ?

In theory, they're pretty much the same, except for the first one not switching between cpu modes twice. I guess it's not much slower, but it wouldn't be faster in any case.