OSDev.org

Posted: **Tue Dec 28, 2004 12:05 pm**

Hi,
I am having trouble enabling paging in my OS. The following list briefly describes the stages I go through before trying to enable paging.

1. Load the boot program, which loads the kernel loader.
2. The kernel loader then: i) enables A20 ii) loads GDT iii) enables protected mode by setting bit 0 in CR0 iV) reprograms PIC and loads IDT.

At this point I create my page directory with 1 table entry mapping the first 4MB of physical address space. I then put the address of the page directory in CR3, which works fine. Then I attempt to set the PE enable bit in CRO, this is when my OS crashes ???

I would like to know if I am following the correct procedures to enable paging or if I am missing something?

Many thanks OS gurus.

Posted: **Tue Dec 28, 2004 12:33 pm**

If all you described is implemented properly, everything should go fine. Did you made sure the "present" bits were correctly set ?

Also, i assume when you talk about "mapping the 1st 4MB" that you simply used a "4MB page" in the page directory (PS=1)...
If that's the case, did you also set the PSE bit in CR4 accordingly and checked that your CPU supports that feature ? if not, the CPU might simply ignore that bit and try to interprete the realmode IVT as being a pagetable %-@

Posted: **Tue Dec 28, 2004 1:02 pm**

Thanks for the reply Pype.Clicker!

I think I have set the present, supervisor etc bits properly. Also, yes I did mean that I added a 4MB page in the page directory.

I'm not to sure about bringing CR4 into the equation since there was not mention of it in the tutorial where I ported my code from (http://osdever.net/tutorials/paging.php?the_id=43)

Here is the paging code I use, which is a direct port from the Bonafide's tutorial (the link for which is given above):

Code: Select all


Page_Directory    equ 0x9C000
Page_Table      equ 0x9D000

[global _read_cr0]
_read_cr0:
   mov eax, cr0
   retn

[global _write_cr0]
_write_cr0:
   push ebp
   mov ebp, esp
   mov eax, [ebp+8]
   mov cr0,  eax
   pop ebp
   retn

[global _read_cr3]
_read_cr3:
   mov eax, cr3
   retn

[global _write_cr3]
_write_cr3:
   push ebp
   mov ebp, esp
   mov eax, [ebp+8]
   mov cr3, eax
   pop ebp
   retn

setup_paging:

   xor ecx,ecx   ;looping increment
   xor eax,eax
   
   ;fill table entry
   .beginloop
   
   or al,3   ;supervisor level, read/write, present(011 in binary)

   mov [Page_Table+(ecx*4)],eax
   
   
   cmp ecx, 0x400      ;compare counter to 1024
   jae .endloop      ;if above or equal jmp to the end
   
   add eax, 0x1000      ;add 4096
   inc ecx
   jmp .beginloop
   
   .endloop
   
   ;fill the first entries
   mov eax, [Page_Table]
   mov [Page_Directory],eax
   
   mov eax,[Page_Directory]
   or al,3
   mov [Page_Directory],eax
   
   ;fill in the other entries
   xor eax,eax
   or al,2
   xor ecx,ecx
   mov ecx,1
   
   .beginloop2
   mov [Page_Directory+(ecx*4)],eax
   
   cmp ecx,0x400
   jae .endloop2
   
   inc ecx
   jmp .beginloop2
   .endloop2
   
   ;update the control registers
   mov eax,0x9C000
   push eax
   call _write_cr3 ;// put that page directory address into CR3

   call _read_cr0
   or eax,0x80000000
   push eax
   call _write_cr0
   ;PAGING enabled!
   


ret

I'm still stuck, so suggestions are still very welcome.

Thanks again Gurus.

Posted: **Tue Dec 28, 2004 5:01 pm**

You need to enable 4Mb pages by setting a bit in CR4 IIRC. Unfortunately I don't have the Intel manuals on hand so I can't tell you which.

Posted: **Wed Dec 29, 2004 2:10 am**

Fraser Gordon wrote: You need to enable 4Mb pages by setting a bit in CR4 IIRC. Unfortunately I don't have the Intel manuals on hand so I can't tell you which.

Having the AMD manuals on hand, which DO deliver the system programming volume, I can tell you that it's bit number 4 in the CR4 register. Note, I tried this too with bochs and it didn't take it any way I tried. The mask you want to OR is thus 010h

Posted: **Wed Dec 29, 2004 7:02 am**

Candy wrote:
Fraser Gordon wrote: You need to enable 4Mb pages by setting a bit in CR4 IIRC. Unfortunately I don't have the Intel manuals on hand so I can't tell you which.
Note, I tried this too with bochs and it didn't take it any way I tried.

also tried with ./configure --enable-4meg-pages ?

Posted: **Wed Dec 29, 2004 8:07 am**

Mr. L wrote: At this point I create my page directory with 1 table entry mapping the first 4MB of physical address space. I then put the address of the page directory in CR3, which works fine. Then I attempt to set the PE enable bit in CRO, this is when my OS crashes ???

So you're using one page directory and one page table to identity map the first 4MB of memory using 4k pages, just like the tutorial you pointed to.

The only thing I can see is that you're incrementing the loop counter after the comparision which I think will make you write one extra page table and page directory entry, that is you end up writing 1025 entries each in your page table and page directory.

The 1025th page table entry would write into the first page directory entry but that's not a problem because you set up the page directory immediately afterwards.

You might want to increment the counter before you do the comparison. I could be wrong though.

Everything else seems to be equivalent to the tutorial you pointed to. The only other thing I can think of is that maybe your GDT and segment registers aren't set up with a base address of 0x0000_0000. You could try printing characters to the screen to indicate how far in the code you get. You could try removing the code to enable paging to see how far it gets.

Posted: **Wed Dec 29, 2004 8:20 am**

you may also wish to run your code in a debugging BOCHS, so that you see where and why it resets. Inspecting memory at 0x9C000 and 0x9D000 from then should be instructive.

http://bochs.sourceforge.net/doc/docboo ... ugger.html

What i suggest is first to find out the value of (r/e)ip at crash and the exception code.

Then restart, use

Code: Select all

vbreak <cs> <eip>
c
dump_cpu
x /4wx 0x9c000
x /1024wx 0x9D000

Posted: **Wed Dec 29, 2004 8:38 am**

WOW! Thanks guys. I'll check into it right away.

Posted: **Wed Dec 29, 2004 12:42 pm**

Ok. I've spent the whole day trying different ways enable paging with no success.

I've tried all the suggestions here with the exception of using Boch's becuase its a real b*****d to configure (I've tried to configure Bochs on many occasions, but now I use Microsoft's virtual PC).

I am still confused as to the origin of this error. I know that a page fault is not occuring becuase my kernel is located at 1MB in physical address space and besides if a page fault does occur my ISR will print some text and halt, which is hasn't done.

Oh well, for the time being this problem has defeated me. ;D I still have much work to do on other areas of my OS.

BTW, thanks for all the help I received, I'll be sure to return to this problem with a vengeance soon.

Posted: **Wed Dec 29, 2004 4:46 pm**

You need to know that under some circumstances, the CPU may even fail to call the page fault handler (for instance if there's a bug with the IDT's page) and will raise double fault. If same error occurs for the double fault handler, the CPU will reset (aka triple fault)

Honestly, in such circumstance, BOCHS is the best tool we have for it can give all the information you need. When patience will come back, i advice you to take time to build a working config ...

Posted: **Wed Dec 29, 2004 4:52 pm**

Pype.Clicker wrote:
Candy wrote: Note, I tried this too with bochs and it didn't take it any way I tried.
Also tried with ./configure --enable-4meg-pages ?

That was in my AMD64 build, which plain requires you to enable that. The AMD64 bit compiled and worked, so I think the other should too. I filed a bug report, got a reply after a year, and at that time I hadn't looked at the bug for a year, so I didn't have the code ready anymore. Might work with new bochs, but not with the one I had.

Posted: **Wed Dec 29, 2004 9:20 pm**

I didn't read all the posts above this very closely, so maybe somebody mentioned this -- but this is one of those pesky details that you can easily overlook...

Somebody correct me if I'm wrong, but I think that when you set the paging flag in CR0 or whatever it is, the CPU is IMMEDIATELY using the new address map, so if your instruction to set the paging flag is at address 5000, and the address of the next instruction is at, say, 5003, then if your page directory maps address 5003 to another physical address in memory, then the CPU just goes off and executes whatever mess is found at the NEW address 5003.

In other words: Make sure, before you set that flag, that the page containing your startup code has a logical address that is the same as the physical address. Make sure that your page directory does NOT map your startup-code page to another address, and make sure that the startup-code page is marked as PRESENT! You can move most of the other pages around and mark them however you like, but you have to be careful not to shoot yourself in the foot when enabling paging.

Posted: **Fri Dec 31, 2004 9:02 am**

OK, I've now managed to get paging working; the reason why it wasn't working before was because my "setup_paging" function was returning a bogus instruction pointer, which was crashing the OS (I discovered this through using Bochs).

Now I'm faced with a slightly less ominous problem: my IDT seems to be working in a roundabout way. I mean, it possible for me to generate interrupts (i.e. through the system timer and keyboard etc), but when a interrupt does occur I get a triple page fault ???

I have a very unsophisticated ISR handler for page faults, which merely prints "PF" to the screen and halts the CPU. However, this routine never gets called during a page fault.
This is what Bochs has to say about it:

00681378250p[CPU ] >>PANIC<< exception(): 3rd (14) exception with no resolution
00681378250i[SYS ] Last time is 1104504378
00681378250i[CPU ] protected mode
00681378250i[CPU ] CS.d_b = 32 bit
00681378250i[CPU ] SS.d_b = 32 bit
00681378250i[CPU ] | EAX=e0000011 EBX=60000011 ECX=00000400 EDX=00000fff
00681378250i[CPU ] | ESP=0008fff8 EBP=00000000 ESI=000006a8 EDI=00000005
00681378250i[CPU ] | IOPL=0 NV UP EI NG NZ NA PE NC
00681378250i[CPU ] | SEG selector base limit G D
00681378250i[CPU ] | SEG sltr(index|ti|rpl) base limit G D
00681378250i[CPU ] | DS:0010( 0002| 0| 0) 00000000 000fffff 1 1
00681378250i[CPU ] | ES:0010( 0002| 0| 0) 00000000 000fffff 1 1
00681378250i[CPU ] | FS:0010( 0002| 0| 0) 00000000 000fffff 1 1
00681378250i[CPU ] | GS:0010( 0002| 0| 0) 00000000 000fffff 1 1
00681378250i[CPU ] | SS:0010( 0002| 0| 0) 00000000 000fffff 1 1
00681378250i[CPU ] | CS:0008( 0001| 0| 0) 00000000 000fffff 1 1
00681378250i[CPU ] | EIP=00100645 (00100645)
00681378250i[CPU ] | CR0=0xe0000011 CR1=0x00000000 CR2=0x00000511
00681378250i[CPU ] | CR3=0x0009c000 CR4=0x00000000
00681378250i[ ] restoring default signal behavior
00681378250i[CTRL ] quit_sim called with exit code 1

Please help.

Thanks, Mr.L

Posted: **Thu Jul 21, 2005 12:32 pm**

Hi, I have some problem with enabling paging.

when my bochs begins paging, it restarted. I wonder if it is anything to do with my bochs. All I know is that when it setcr0 or it with 0x8000 0000. It then stopped.

I put the page directory in 0x9C000; and 9D000 for page table. And my I don't know why in there. Thinking if it has anything to do with that.

Grub also tells me that:
num_of_entry = 10, size = 0x28, addr = 0x104000, shndx = 0x7
mmap_addr = 0x2CAE8, mmap_length = 0x30
size = 0x14, base_addr = 0x00, length = 0x09FC00, type = 0x1
size = 0x14, base_addr = 0x0100000, length = 0x01FF00000, type = 0x1
cr0:0x60000011 cr3:0x0 cs:0x8 ds:0x10 ss:0x10
es:0x10 fs:0x10 gs:0x10
ebp:0x103270 esp:0x10320C esi:0x2CB46 edi:0x103C60
eax:0x2CA20 ebx:0x2CA20 ecx:0x0 edx:0x3D5

Please help~!

Here is my bochs info that where the problem is:

00000000000i[ ] Bochs x86 Emulator 2.1.1
00000000000i[ ] February 08, 2004
00000000000i[ ] System configuration
00000000000i[ ] processors: 1
00000000000i[ ] A20 line support: yes
00000000000i[ ] APIC support: no
00000000000i[ ] CPU configuration
00000000000i[ ] level: 5
00000000000i[ ] fpu support: yes
00000000000i[ ] paging support: yes, tlb enabled: yes
00000000000i[ ] mmx support: yes
00000000000i[ ] sse support: no
00000000000i[ ] v8086 mode support: yes
00000000000i[ ] 3dnow! support: no
00000000000i[ ] PAE support: no
00000000000i[ ] PGE support: no
00000000000i[ ] PSE support: no
00000000000i[ ] x86-64 support: no
00000000000i[ ] SEP support: no
00000000000i[ ] Optimization configuration
00000000000i[ ] Guest2HostTLB support: yes
00000000000i[ ] RepeatSpeedups support: yes
00000000000i[ ] Icache support: yes
00000000000i[ ] Host Asm support: yes

Thanks in advances

OSDev.org

Enabling Paging

Enabling Paging

Re:Enabling Paging

Re:Enabling Paging

Re:Enabling Paging

Re:Enabling Paging

Re:Enabling Paging

Re:Enabling Paging

Re:Enabling Paging

Re:Enabling Paging

Re:Enabling Paging

Re:Enabling Paging

Re:Enabling Paging

Re:Enabling Paging

Re:Enabling Paging

Re:Enabling Paging